500 MHz, Linear-in-dB VGA
with AGC Detector
AD8367
FEATURES
Broad-range analog variable gain: −2.5 dB to +42.5 dB
3 dB cutoff frequency of 500 MHz
Gain up and gain down modes
Linear-in-dB, scaled 20 mV/dB
Resistive ground referenced input
Nominal Z
IN
= 200 Ω
On-chip, square-law detector
Single-supply operation: 2.7 V to 5.5 V
FUNCTIONAL BLOCK DIAGRAM
VPSI
12
VPSO
11
ENBL
2
14
ICOM
ICOM
1
INPT
3
AD8367
9-STAGE ATTENUATOR BY 5dB
BIAS
9
DECL
13
HPFL
g
m
CELLS
SQUARE
LAW
DETECTOR
10
VOUT
GAUSSIAN INTERPOLATOR
ICOM
7
8
4
5
6
OCOM
02710-001
APPLICATIONS
Cellular base stations
Broadband access
Power amplifier control loops
Complete, linear IF AGC amplifiers
High speed data I/O
MODE
GAIN
DETO
Figure 1.
GENERAL DESCRIPTION
The AD8367 is a high performance 45 dB variable gain
amplifier with linear-in-dB gain control for use from low
frequencies up to several hundred megahertz. The range,
flatness, and accuracy of the gain response are achieved using
Analog Devices’ X-AMP® architecture, the most recent in a
series of powerful proprietary concepts for variable gain
applications, which far surpasses what can be achieved using
competing techniques.
The input is applied to a 9-stage, 200 Ω resistive ladder network.
Each stage has 5 dB of loss, giving a total attenuation of 45 dB.
At maximum gain, the first tap is selected; at progressively
lower gains, the tap moves smoothly and continuously toward
higher attenuation values. The attenuator is followed by a
42.5 dB fixed gain feedback amplifier—essentially an
operational amplifier with a gain bandwidth product of
100 GHz—and is very linear, even at high frequencies. The
output third order intercept is +20 dBV at 100 MHz (+27 dBm,
re 200 Ω), measured at an output level of 1 V p-p with V
S
= 5 V.
The analog gain-control input is scaled at 20 mV/dB and runs
from 50 mV to 950 mV. This corresponds to a gain of −2.5 dB
to +42.5 dB, respectively, when the gain up mode is selected and
+42.5 dB to −2.5 dB, respectively, when gain down mode is
selected. The gain down, or inverse, mode must be selected
when operating in AGC in which an integrated square-law
detector with an internal setpoint is used to level the output to
354 mV rms, regardless of the crest factor of the output signal.
A single external capacitor sets up the loop averaging time.
The AD8367 can be powered on or off by a voltage applied to
the ENBL pin. When this voltage is at a logic LO, the total
power dissipation drops to the milliwatt range. For a logic HI,
the chip powers up rapidly to its normal quiescent current of
26 mA at 25°C. The AD8367 is available in a 14-lead TSSOP
package for the industrial temperature range of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8367
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Input Attenuator and Gain Control ......................................... 11
Input and Output Interfaces...................................................... 11
Power and Voltage Metrics........................................................ 12
Noise and Distortion.................................................................. 12
Output Centering ....................................................................... 12
RMS Detection ........................................................................... 13
Applications..................................................................................... 14
Input and Output Matching...................................................... 14
VGA Operation .......................................................................... 15
Modulated Gain Mode .............................................................. 15
AGC Operation .......................................................................... 15
Modifying the AGC Setpoint.................................................... 16
Evaluation Board ........................................................................ 19
Characterization Setup and Methods ...................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 3............................................................................ 6
Changes to Figure 8.......................................................................... 7
Changes to Figure 9, Figure 12, and Figure 14 ............................. 8
Changes to Input and Output Interfaces Section ....................... 11
Changes to Output Centering Section and Figure 31................ 12
Changes to RMS Detection Section ............................................. 13
Changes to Figure 32, Table 4, and Table 5 ................................. 14
Changes to Figure 33, Figure 34, and
AGC Operation Section................................................................. 15
Changes to the Modifying the AGC Set Point Section.............. 16
Changes to Figure 38...................................................................... 17
Changes to Figure 42...................................................................... 19
Changes to Table 7.......................................................................... 20
Moved Table 7 to Page ................................................................... 20
Moved Characterization Setup and Methods Section to Page . 20
Moved Figure 45 to Page ............................................................... 20
Changes to Ordering Guide .......................................................... 21
Updated Outline Dimensions ....................................................... 21
10/01—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8367
SPECIFICATIONS
V
S
= 5 V, T
A
= 25°C, system impedance Z
O
= 200 Ω, V
MODE
= 5 V, f = 10 MHz, unless otherwise noted.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
GAIN Range
INPUT STAGE
Maximum Input
Input Resistance
GAIN CONTROL INTERFACE
Scaling Factor
Gain Law Conformance
Maximum Gain
Minimum Gain
V
GAIN
Step Response
Small Signal Bandwidth
OUTPUT STAGE
Maximum Output Voltage Swing
Output Source Resistance
Output Centering Voltage
1
SQUARE LAW DETECTOR
Output Set Point
AGC Small Signal Response Time
POWER INTERFACE
Supply Voltage
Total Supply Current
Disable Current vs. Temperature
MODE CONTROL INTERFACE
Mode LO Threshold
Mode HI Threshold
ENABLE INTERFACE
Enable Threshold
Enable Response Time
Enable Input Bias Current
f = 70 MHz
Gain
Gain Scaling Factor
Gain Intercept
Noise Figure
Output IP3
Output 1 dB Compression Point
Conditions
Min
LF
45
Pins INPT and ICOM
To avoid input overload
From INPT to ICOM
Pin GAIN
V
MODE
= 5 V, 50 mV ≤ V
GAIN
≤ 950 mV
V
MODE
= 0 V, 50 mV ≤ V
GAIN
≤ 950 mV
100 mV ≤ V
GAIN
≤ 900 mV
V
GAIN
= 0.95 V
V
GAIN
= 0.05 V
From 0 dB to 30 dB
From 30 dB to 0 dB
V
GAIN
= 0.5 V
Pin VOUT
R
L
= 1 kΩ
R
L
= 200 Ω
Series resistance of output buffer
Pin DETO
C
AGC
= 100 pF, 6 dB gain step
Pins VPSI, VPSO, ICOM, and OCOM
2.7
ENBL high, maximum gain, R
L
= 200 Ω
(includes load current)
ENBL low
−40°C ≤ TA ≤ +85°C
Pin MODE
Device in negative slope mode of operation
Device in positive slope mode of operation
Pin ENBL
Time delay following LO to HI transition until
device meets full specifications.
ENBL at 5 V
ENBL at 0 V
Maximum gain
Minimum gain
26
1.3
354
1
5.5
30
1.6
1.8
mV rms
μs
V
mA
mA
mA
V
V
V
μs
μA
nA
dB
dB
mV/dB
dB
dB
dBm
dBV rms
dBm
dBV rms
700
200
+20
−20
±0.2
+42.5
−2.5
300
300
5
4.3
3.5
50
V
S
/2
Typ
Max
500
Unit
MHz
dB
mV p-p
Ω
mV/dB
mV/dB
dB
dB
dB
ns
ns
MHz
V p-p
V p-p
Ω
V
175
225
1.2
1.4
2.5
1.5
27
32
+42.5
−3.7
19.9
−5.6
6.2
36.5
29.5
8.5
1.5
Maximum gain
f1 = 70 MHz, f2 = 71 MHz, V
GAIN
= 0.5 V
V
GAIN
= 0.5 V
Rev. A | Page 3 of 24
AD8367
Parameter
f = 140 MHz
Gain
Gain Scaling Factor
Gain Intercept
Noise Figure
Output IP3
Output 1 dB Compression Point
f = 190 MHz
Gain
Gain Scaling Factor
Gain Intercept
Noise Figure
Output IP3
Output 1 dB Compression Point
f = 240 MHz
Gain
Gain Scaling Factor
Gain Intercept
Noise Figure
Output IP3
Output 1 dB Compression Point
Conditions
Maximum gain
Minimum gain
Min
Typ
+43.5
−3.6
19.7
−5.3
7.4
32.7
25.7
8.4
1.4
+43.5
−3.8
19.6
−5.3
7.5
30.9
23.9
8.4
1.4
+43
−4.1
19.7
−5.2
7.6
29.2
22.2
8.1
1.1
Max
Unit
dB
dB
mV/dB
dB
dB
dBm
dBV rms
dBm
dBV rms
dB
dB
mV/dB
dB
dB
dBm
dBV rms
dBm
dBV rms
dB
dB
mV/dB
dB
dB
dBm
dBV rms
dBm
dBV rms
Maximum gain
f1 = 140 MHz, f2 = 141 MHz, V
GAIN
= 0.5 V
V
GAIN
= 0.5 V
Maximum gain
Minimum gain
Maximum gain
f1 = 190 MHz, f2 = 191 MHz, V
GAIN
= 0.5 V
V
GAIN
= 0.5 V
Maximum gain
Minimum gain
Maximum gain
f1 = 240 MHz, f2 = 241 MHz, V
GAIN
= 0.5 V
V
GAIN
= 0.5 V
1
The output dc centering voltage is normally set at V
S
/2 and can be adjusted by applying a voltage to DECL.
Rev. A | Page 4 of 24
AD8367
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPSO, VPSI
ENBL Voltage
MODE Select Voltage
V
GAIN
Control Voltage
Input Voltage
Internal Power Dissipation
θ
JA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 60 sec)
Rating
5.5 V
V
S
+ 200 mV
V
S
+ 200 mV
1.2 V
±600 mV
250 mW
150°C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 24
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