RT9005A/B
DDR VDDQ and Termination Voltage Regulator
General Description
The RT9005A/B is
a dual-output linear regulator for DDR-
SDRAM VDDQ supply and termination voltage VTT supply.
The Regulator is capable of actively sinking or sourcing
up to 2A. The output termination voltage can be tightly
regulated to track 1/2 VDDQ by two external voltage divider
resistors.
Features
Ideal for DDR-I and DDR-II VDDQ, VTT Applications
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
High Accuracy Output Voltage at Full-Load
VOUT2 Sink and Source 2A Continuous Current
VOUT2 Adjustment by Two External Resistors
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in SOP-8 (Exposed Pad) Packages
RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT9005
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
VOUT1 Output Voltage
A : 2.5V
B : 1.8V
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Applications
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I and DDR-II Memory Systems
Pin Configurations
(TOP VIEW)
BP
VIN1
VIN2
VCNTL
2
3
4
8
7
GND
6
9
5
VOUT1
GND
VOUT2
VREFEN
SOP-8 (Exposed Pad)
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RT9005A/B
Typical Application Circuit
V
IN1
C
IN1
2.2uF
C
BP
10nF
2
VIN1
1 BP
8 VOUT1
R1
C
OUT1
2.2uF
RT9005A/B
VOUT2 6
C
OUT2
470uF
3
VIN2
VCNTL
4
C
IN2
470uF
V
CTNL
= 3.3V
C
VCNTL
47uF
R
TT
V
IN2
V
OUT1
2N7002
EN
R2
C
SS
1uF
5 VREFEN
GND
7,
Exposed Pad(9)
GND
Note :
If there is any application need to use 10μF ceramic capacitor in front of R
TT
, please shut one 1000μF (Aluminum
eletrolytic capacitor).
Functional Pin Description
Pin No.
1
7,
9 (Exposed Pad)
2
Pin Name
BP
Pin Function
Noise Reduction. Connecting a 10nF capacitor to GND to reduce output noise.
Common Ground (The exposed pad must be soldered to a large PCB and
GND
connected to GND for maximum power dissipation). The GND pad are a should be
as large as possible and using many vias to conduct the heat into the buried GND
plate of PCB layer.
Linear Regulator Power Input Voltage.
Input voltage which supplies current to the output pin. Connect this pin to a
3
VIN2
well-decoupled supply voltage. To prevent the input rail from dropping during large
load transient, a large, low ESR capacitor is recommended to use. The capacitor
should be placed as close as possible to the VIN2 pin.
VCNTL supplies the internal control circuitry and provides the drive voltage. The
4
VCNTL
driving capability of output current is proportioned to the VCNTL. Connect this pin
to 3.3V bias supply to handle large output current with at least 10uF capacitor from
this pin to GND.
Reference voltage input and active low VOUT2 shutdown control pin. Two resistors
dividing down the VIN voltage on the pin to create the regulated output voltage.
Pulling the pin to ground turns off the device by an open-drain, such as 2N7002,
signal N-MOSFET.
Regulator Output. VOUT2 is regulated to REFEN voltage that is used to terminate
the bus resistors. It is capable of sinking and sourcing current while regulating the
6
VOUT2
output rail. To maintain adequate large signal transient response, typical value of
1000μF AL electrolytic capacitor with 10μF ceramic capacitors are recommended
to reduce the effects of current transients on V
OUT
.
8
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2
VIN1
5
VREFEN
VOUT1
Regulator 2.5V/1.8/1.5V Output.
DS9005A/B-03 April 2011
RT9005A/B
Function Block Diagram
VIN1
Current Limit
Sensor
+
Error
-
Amplifier
-
+
VCNTL
VOUT1
Thermal
Shutdown
BP
0.8V
Reference
VCNTL
VIN2
Current Limit
Thermal Protection
GND
+
VREFEN
VOUT2
-
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RT9005A/B
Absolute Maximum Ratings
(Note 1)
6V
1.33W
75°C/W
28°C/W
150°C
Supply Input Voltage, V
IN
------------------------------------------------------------------------------------------
Power Dissipation, P
D
@ T
A
= 25°C
SOP-8 (Exposed) ----------------------------------------------------------------------------------------------------
Package Thermal Resistance (Note 2)
SOP-8 (Exposed),
θ
JA
----------------------------------------------------------------------------------------------
SOP-8 (Exposed),
θ
JC
----------------------------------------------------------------------------------------------
Junction Temperature -----------------------------------------------------------------------------------------------
Lead Temperature (Soldering, 10sec.) -------------------------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------------------------
−
65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions
(Note 4)
Supply Input Voltage, V
IN1
----------------------------------------------------------------------------------------- 5V to 2.5V
Supply Input Voltage, V
IN2
----------------------------------------------------------------------------------------- 3.6V to 1.5V
Control Voltage, V
CNTL
---------------------------------------------------------------------------------------------- 5V to 3.1V
Junction Temperature Range --------------------------------------------------------------------------------------
−40°C
to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------------
−40°C
to 85°C
Electrical Characteristics
(V
IN1
=3.3V , V
IN1
= V
OUT
+ 1V, C
IN1
= C
OUT1
= 2.2μF (Ceramic) & C
BP
= 10nF; V
IN2
= 2.5V/1.8/1.5V, V
CNTL
= 3.3V, V
REFEN
= 1.25V/
0.9/0.75V, C
IN2
= 470μF, C
VCNTL
= 47μF, C
OUT2
= 1000μF(Electrolytic), T
A
= 25°C, unless otherwise specified)
Parameter
Input
Operation Current
Standby Current
VOUT1 (VDDQ)
VOUT1 Accuracy
VOUT1 Current Limit
VOUT1 Dropout Voltage
(Note 6)
Line Regulation
Load Regulation
VOUT2 (VTT)
Output Offset Voltage
(Note 7)
(Note 5)
Symbol
I
VCNTL
I
STBY2
I
OUT
= 0A
Test Conditions
Min
--
--
Typ
1.5
50
Max
3.0
90
Unit
mA
uA
V
REFEN
<
0.2V (Shutdown),
R
LOAD
= 180Ω
I
OUT
= 10mA
R
LOAD
= 0.5Ω, V
IN1
= 3.3V
I
OUT
= 0.5A
I
OUT
= 1.0A
V
IN1
= (V
OUT1
+ 0.5V) to 5.5V
I
OUT1
= 1mA
V
IN1
= (V
OUT1
+ 0.5V)
10mA < I
OUT1
< 1A
I
OUT
= 0A
ΔV
OUT
I
LIM1
V
DROP
ΔV
LINE
ΔV
LOAD
−2
2
--
--
--
--
--
2.8
120
240
--
0.4
+2
3
180
360
0.3
--
V
A
mV
%
%/A
(Note 8) V
OS
−20
--
+20
mV
To be continued
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DS9005A/B-03 April 2011
RT9005A/B
Parameter
Load Regulation
(Note 7)
Symbol
ΔV
LOAD
I
LIM2
I
OUT
= +2A
I
OUT
=
−2A
Test Conditions
Min
−20
2.2
--
--
Enable
Shutdown
0.6
--
Typ
--
--
170
35
--
--
Max
+20
--
--
--
--
0.2
Unit
mV
A
°C
°C
VOUT2 Current Limit
Protection
Thermal Shutdown Temperature T
SD
Thermal Shutdown Hysteresis
REFEN Shutdown
Shutdown Threshold
V
IH
V
IL
ΔT
SD
V
Note 1.
Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2.
θ
JA
is measured in the natural convection at T
A
= 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of
θ
JC
is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 3.
Devices are ESD sensitive. Handling precaution is recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Note 5.
V
OUT2
Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown
signal on REFEN pin (V
IL
< 0.2V). It is measured with V
IN2
= V
CNTL
= 5V.
Note 6.
The dropout voltage is defined as V
IN
-V
OUT
, which is measured when V
OUT
is V
OUT(NORMAL)
−
100mV.
Note 7.
Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
Note 8.
V
OS
offset is the voltage measurement defined as V
OUT
subtracted from V
REFEN
.
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