P4C1257/P4C1257L
ULTRA HIGH SPEED 256K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 12/15/20/25 ns (Industrial)
– 25/35/45/55/70 ns (Military)
Single 5V±10% Power Supply
Data Retention with 2.0V Power Supply
(P4C1257L)
Separate Data I/O
Three-State Output
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
– 28-Pin Flatpack
DESCRIPTIOn
The P4C1257/P4C1257L are 256Kx1-bit ultra high-speed
static RAMs. The CMOS memories require no clocks or
refreshing and have equal access and cycle times. The
RAMs operate from a single 5V ± 10% tolerance power
supply. Data integrity is maintained for supply voltages
down to 2.0V, typically drawing 10µA.
Access times as fast as 12 nanoseconds are available,
greatly enhancing system speeds.
The P4C1257/P4C1257L are available in 24-pin 300 mil
DIP and SOJ, 28-pin LCC and Flatpack packages, provid-
ing excellent board level densities.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P4, C4)
SOJ (J4)
LCC (L5)
Document #
SRAM137
REV 01
Revised June 2013
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
8
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C1257
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
MIL
IND/COM
MIL
IND/COM
P4C1257L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
2.4
Unit
V
V
V
V
V
V
V
Input Clamp Diode Voltage V
CC
= Min, I
IN
= -18 mA
Output Low Voltage (TTL
Load)
Output High Voltage (TTL
Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min
I
OH
= -4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
-10
-5
-10
-5
+10
+5
+10
+5
95
-10
-5
-10
-5
+10
µA
+5
+10
µA
+5
85
mA
I
LI
I
LO
Output Leakage Current
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
V
CC
=Max, I
OUT
=0 mA, f=Max
CE
≥ V
IH
, V
CC
= Max, f = Max,
Outputs Open
CE
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
CC
Operating Supply Current
Standby Power Supply
Current (TTL Input Levels)
MIL
IND/COM
MIL
IND/COM
—
—
—
—
25
25
20
10
—
—
—
—
25
mA
25
3
mA
3
I
SB
I
SB1
Standby Power Supply
Current (CMOS Input
Levels)
N/A = Not applicable
Document #
SRAM137
REV 01
Page 2
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
DATA RETEnTIOn CHARACTERISTICS (P4C1257L)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
≥ V
CC
-0.2V,
V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
600
900
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
Parameter
Read Cycle
Time
Address Ac-
cess Time
Chip Enable
Access Time
Output Hold
from Address
Change
Chip Enable
to Output in
Low Z
Chip Disable
to Output in
High Z
Chip Enable
to Power Up
Time
Chip Disable to
Power Down
0
12
2
-12
Min
12
12
12
2
Max
Min
15
15
15
2
-15
Max
Min
20
20
20
2
-20
Max
Min
25
25
25
2
-25
Max
Min
35
35
35
2
-35
Max
Min
45
45
45
2
-45
Max
Min
55
55
55
2
-55
Max
Min
70
70
70
-70
Max
Unit
ns
ns
ns
ns
t
LZ
2
2
2
2
2
2
2
2
ns
t
HZ
6
8
10
12
17
20
25
30
ns
t
PU
t
PD
0
15
0
20
0
25
0
35
0
45
0
55
0
70
ns
ns
TIMIng WAVEFORM OF READ CYCLE nO. 1 (ADDRESS COnTROLLED)
(5,6)
Document #
SRAM137
REV 01
Page 3
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
TIMIng WAVEFORM OF READ CYCLE nO. 2 (CE COnTROLLED)
(5,7,8)
DATA RETEnTIOn WAVEFORM
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
Parameter
Write Cycle
Time
Chip Enable
Time to End of
Write
Address Valid
to End of Write
Address Setup
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
Data Hold
Time
Write Enable
to Output in
High Z
Output Active
from End of
Write
0
-12
Min
8
7
7
0
7
0
6
0
5
Max
Min
10
8
8
0
8
0
7
0
6
-15
Max
Min
12
10
10
0
10
0
8
0
7
-20
Max
Min
15
12
12
0
12
0
10
0
8
-25
Max
Min
20
15
15
0
15
0
12
0
10
-35
Max
Min
25
18
18
0
18
0
15
0
15
-45
Max
Min
35
25
25
0
20
0
20
0
15
-55
Max
Min
45
30
30
0
25
0
25
0
20
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
OW
0
0
0
0
0
0
0
ns
Document #
SRAM137
REV 01
Page 4
P4C1257/P4C1257L - ULTRA HIGH SPEED 256K X 1 STATIC CMOS RAMS
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(10,11)
TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED)
(10)
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM137
REV 01
Page 5
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