New Features
NV DAC
NV DAC with Selectable Output Range and Memory
FEATURES
• 12-Bit Resolution
• Selectable full scale and zero scale voltages
• Optional External full scale and zero scale
references
• Programmable, non-volatile DAC initial value
register
• Optional UP/DOWN interface
• Guaranteed Monotonic Operation, <0.5LSB DNL
• Buffered Output Option
• Integrated Voltage Reference Option
• Voltage Reference Output (1.21V) Option
• 6 µs settling time, full scale
• SPI interface, 5MHz
• Up to 5 slave Address Pins
• Power up recall and ready output
• 56 Bytes of general purpose EEPROM
• Asynchronous clear pin and control bit
• V
CC
= 5V ±10%
• 20-lead TSSOP
DESCRIPTION
X79000/X79001/X79002
The X79000 is a family of Single Channel Non-Volatile
(NV) Digital-to-Analog Converters with integrated voltage
reference, configurable output buffer, general purpose
EEPROM, and selectable full scale and zero offset
voltages.
The X79000 series implements an SPI serial bus
interface with slave address identification allowing up to
32 devices on some options. The full scale and zero
scale voltages and the DAC initial value register can be
set via the SPI bus interface. Optional pins are provided
for Up/Down style interface allowing for increment and
decrement of the DAC register in 1, 4, or 16 steps at a
time.
A Power On Recall circuit is implemented to keep the
DAC output at high impedance on power up and to load
an initial user defined value from non-volatile memory. A
power up ready signal is provided to alert the system to
begin operations.
Additional general purpose non-volatile memory (56
Bytes) is provided for curve-fit profile setting, signal
conditioning parameters, or device and system
indentification.
X79000 FUNCTIONAL DIAGRAM
Vcc
Vss
VH VL
Vout
Vref
Voltage
Reference
Power Up
Logic
VFB
A[2:0]
SCK
SO
SI
CS
Serial
Interface
and
Control
Logic
General
Purpose
EEPROM
DAC Initial
Value Register
DAC Register
CLR
DAC Shift
Register
UP
DOWN
Variable Gain
& Level Shift
Variable Gain
& Level Shift
DAC
Core
OE
+
Vbuf
–
RDY
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X79000/X79001/X79002
X79001 / X79002 FUNCTIONAL DIAGRAM
Vcc
Vss
VH VL
Vcc
Vss
VH VL
Vout
Voltage
Reference
Power Up
Logic
Variable Gain
& Level Shift
Variable Gain
& Level Shift
DAC
Core
OE
+
Vbuf
–
RDY
VFB
A[5:0]
SCK
SO
SI
CS
Serial
Interface
and
Control
Logic
General
Purpose
EEPROM
DAC Register
A[4:0]
SCK
DAC Initial
Value Register
DAC Shift
Register
CLR
SO
SI
CS
Serial
Interface
and
Control
Logic
General
Purpose
EEPROM
DAC Register
Power Up
Logic
Vref
Voltage
Reference
Variable Gain
& Level Shift
Variable Gain
& Level Shift
DAC
Core
Vout
RDY
CLR
DAC Initial
Value Register
DAC Shift
Register
UP
DOWN
X79001
X79002
PIN CONFIGURATION
TSSOP
SCK
A0
A1
A2
SI
SO
RDY
UP
DOWN
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TSSOP
CS
CLR
V
CC
VH
VL
Vref
V
SS
Vout
Vbuf
VFB
CLR
CS
SCK
A0
A1
A2
SI
SO
RDY
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TSSOP
V
CC
A3
VH
VL
A4
A5
V
SS
Vout
Vbuf
VFB
CS
SCK
A0
A1
A2
SI
SO
RDY
UP
DOWN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
V
CC
A3
VH
VL
Vref
A4
V
SS
Vout
DNC
X79000
X79001
DNC = Do Not Connect
X79002
ORDERING INFORMATION
Features
Voltage References
Zero Scale Voltage
Input/Output (VL)
Full Scale Voltage
Input/Output (VH)
Voltage Ref
Output Pin (Vref)
Voltage
Outputs
Buffered Out
(Vbuf) and Buffer
Feedback (VFB)
with Enable (OE)
DAC Control
System
Control
Power Ready (RDY)
Y
Y
Y
Device
X79000V20I
X79001V20I
X79002V20I
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
Y
A0, A1, A2
A0, A1, A2, A3, A4, A5
A0, A1, A2, A3, A4
Notes:
Y = Yes, N = No
*All options are for 12-bit resolution, industrial temperature operating range, and a 20-pin TSSOP package.
Slave
Address Pins
Increment/
Decrement
(UP,DOWN)
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X79000/X79001/X79002
PIN DESCRIPTIONS
Pin Name
CS
SCK
SI
SO
RDY
CLR
A5, A4, A3,
A2, A1, A0
OE
UP
DOWN
V
CC
V
SS
Vout
Vbuf
VFB
Vref
VH
VL
DNC
Pin Description
SPI Chip Select. CMOS Input Pin. Active low.
SPI Clock. CMOS Input Pin, with hysteresis.
SPI Serial Data. CMOS Input Pin, with hysteresis.
SPI Serial Data Output Pin. CMOS levels with high impedance state.
Power-Up “Ready” Indicator Output Pin. Active low. Open drain output.
Clear DAC Volatile Register Input Pin. Active high. CMOS Input Pin with hysteresis. On-chip pulldown.
SPI Address Input pins. CMOS Input Pins. On-chip pulldowns.
Buffer Output Enable Input Pin. Active high. CMOS Input Pin with hysteresis. On-chip pulldown.
UP Input pin of the UP/DOWN interface. CMOS Input Pin with deglitching filter. On-chip pulldown.
DOWN Input pin of the UP/DOWN interface. CMOS Input Pin with deglitching filter. On-chip pulldown.
Power Supply Pin.
Ground Pin.
Unbuffered DAC Output Pin.
Buffered DAC Output Pin.
Feedback Pin for Buffer Stage.
Bandgap Voltage Output Pin.
Full Scale Voltage Input or Output Pin.
Zero Scale Voltage Input or Output Pin.
Do Not Connect
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X79000/X79001/X79002
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to Vss
Temperature under bias ........................–40°C to 85°C
Storage temperature .........................–65°C to +150°C
Voltage on every pin except Vcc.............. –0.5V to +7V
Voltage on Vcc Pin .................................... –0.5V to 6V
D.C. Output Current at pins SO and RDY ............ 5 mA
D.C. Output Current at pins VL, VH,
VFB, Vout and Vref............................. –0.50 to 1 mA
VBUF output short circuit duration ............ 10 seconds
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Temperature
Voltage on Vcc Pin
Voltage on any other Pin
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or an other conditions above those listed
in the operational sections of this specification) is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Min.
–40
4.5
–0.3
Max.
+85
5.5
Vcc +0.3
Units
°C
V
V
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, all typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and mini-
mum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss.
All bits in control registers are “0”. SPI interface in “standby” (see notes 1 and 2 on page 6). Output pins unloaded. Input
pins floating. DAC input is 000hex.)
Parameter
Buffered DAC and Reference
Resolution
INL
DNL
Total Offset Error
Total Fullscale Error
Total Offset Error Drift
Total Fullscale Error Drift
Settling time to 1 LSB
Buffer Only
Output Buffer Offset
Output Buffer Offset Drift
DC PSRR
Vbuf output slew rate
Output Buffer 3dB Bandwidth
Digital feed through
Output load regulation
Short circuit current @ Vbuf
Capacitive Loading Stability
Min
Typ
12
Max
Units
bit
LSB
LSB
mV
mV
ppm/°C
ppm/°C
µs
µs
mV
µV/°C
mV/V
V/µs
kHz
nV•sec
mV/mA
mA
pF
Notes
–0.5
±10
0.5
12
22
50
50
2
6
(1), (2), (3), VL = 0.151V, VH = 3.025V
(1), (2), (4), VL = 0.151V, VH = 3.025V
(1), (2), (4), VL = 0.151V, VH = 3.025V
Step size
≤
100mV, (2), (5)
Step size up to full scale, (2), (5)
150mV < Vout < V
CC
– 150mV
(5)
(5)
150mV < (V(VFB) =
V(Vbuf)) < V
CC
– 150mV (5)
(6)
140mV
≤
V(Vbuf)
≤
V
CC
-140mV
I(Vbuf) = ±1mA
V(Vbuf) = V
CC
or 0V
Rload
≥
2k
Ω
(5)
10
30
6
20
+1.5
-6
-20
-1.5
0.2
300
1000
10
–1
50
100
1
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X79000/X79001/X79002
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Reference
Vrefout
TCOref
R
VHVL
t
OEVALID
t
OEDIS
C
out
C
in
Output Voltage at VRef at 25°C
Temperature coefficient of VRef
output voltage
Resistance between VL and VH
OE rising edge to output valid
delay
OE falling edge to high impedance
output delay
SO and RDY pin capacitance
CLR, CS, SCK, A0, A1, A2, A3,
A4, A5, SI, UP, DOWN, OE
pin capacitance
On-chip pull down current at A0,
A1, A2, A3, A4, A5, UP, DOWN,
and CLR
CS, SCK and SI input Low voltage
CS, SCK and SI input High voltage
CS, CLK and SI input current
SO output High voltage
SO Output Low Voltage
SO output High impedance current
RDY and SO output Low voltage
RDY output High current
CLR, OE, UP, DOWN, A0, A1, A2,
A3, A4, and A5 input Low voltage
CLR, OE, UP, DOWN, A0, A1, and
A2 input High voltage
CS, SI, SCK, CLR, OE, UP and
DOWN input hysteresis
Standby current into Vcc pin
Full operation current into Vcc pin
0
1
9
1.20
1.21
50
11.4
14
100
100
10
8
1.22
V
ppm/
˚C
k
Ω
µs
µs
pF
pF
Voltage at pin of 0V or Vcc. 1
MHZ signal. (4)
–20µA < I(VRef) < 0,
Vref as an output
(5)
VH & VL external
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
Digital Interface
I
PLDN
20
µA
Voltage at the pin between 0V
and Vcc
V
ILSPI
V
IHSPI
I
INSPI
V
OHSO
V
OLSO
I
OZSO
V
OLSO
I
OHRDY
V
ILCMOS
V
IHCMOS
V
HYST
-0.8
0.8 x
Vcc
-1
Vcc-
0.4
0
-20
0
0
-0.3
0.8 x
Vcc
0.5
0.2 x
Vcc
Vcc +
0.3
10
Vcc
0.4
+20
0.4
100
0.2 x
Vcc
Vcc +
0.3
V
V
µA
V
V
µA
V
µA
V
V
V
Voltage at the pin between 0V
and Vcc
I(SO) = -2mA
I(SO) = 2mA
V(SO) between 0 and Vcc
I(SO) or I(RDY) = 2 mA
V(RDY) = Vcc
(5)
Power Requirements
Iccstby
Iccfull
2.5
3
mA
mA
V(SCK) = V(SI) = 0 V, V(CS) =
Vcc
2-wire interface reading from
memory, 2.5 MHz clock at SCK,
V(OE) = V
CC
, VFB = VBUF (2)
Average during internal
non-volatile write cycle
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Iccwrite
Nonvolatile Write current into Vcc
pin
3
mA
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