monitor identification, including recovery to DDC1
- Low power CMOS technology
- 1 mA typical active current
- 10 uA standby current typical at 5.5V
- 2-wire serial interface bus, I
2
C compatible
- 100Khz (2.5V) and 400Khz (5V) compatibility
- Self-timed write cycle (including auto-erase)
- Hardware write-protect pin
- Page-write buffer for up to eight bytes
- 1,000,000 erase/write cycles
- Data retention > 40 years
- 8-pin PDIP and SOP packages
- Available for extended temperature ranges
Commercial (C): 0°C to +70°C
Industrial (I): -40°C to +85°C
(Preliminary)
General Description
The AM24LC21B is a 128 x 8-bit dual-mode
Electrically Erasable PROM. This device is
designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been
implemented: transmit only mode and bi-directional
mode. Upon power-up, the device will be in the
transmit only mode, sending a serial bit stream of
the memory array contents, clocked by the VCLK
pin. A valid high to low transition on the SCL pin will
cause the device to enter the bi-directional mode,
with byte selectable read/write capability of the
memory array. The AM24LC21B is available in a
standard 8-pin PDIP and SOP package in both
commercial and industrial temperature ranges.
The
difference
between
AM24LC21
and
AM24LC21B is the former has Write protection
function and the latter doesn’t have write protection
function.
Pin Assignments
(Top View)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
NC
NC
NC
VSS
1
2
3
4
(Top View)
8
7
6
5
VCC
VCLK
SCL
SDA
Pin Descriptions
Name
NC
VSS
SDA
VCLK
VCC
SCL
Description
No connection
Ground
Serial address/data I/O
Serial clock (transmit only mode)
Power supply
Serial clock (bi-directional mode)
PDIP Package
SOP Package
Note.
See pin descriptions (continued) at page 11/13 for more
detailed
Ordering Information
AM24LC 21B X X X
Operating Voltage
LC : 2.5V~5.5V,CMOS
Type
1K Dual Mode
Temp. grade
Blank : 0
o
C ~
+
70
o
C
I
o
o
:
−
40 C ~
+
85 C
Package
S : SOP-8L
N : PDIP-8L
Packing
Blank : Tube
A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.1 Jul 2, 2003
1/13
AM24LC21B
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
Block Diagram
SDA
SCL
I/O
control logic
HV generator
(Preliminary)
VCLK
EEPROM
Array
Page latches
XDec
Memory
control logic
VCC
YDec
VSS
Sense AMP
R/W* control
Anachip Corp.
www.anachip.com.tw
2/13
Rev 0.1 Jul 2, 2003
AM24LC21B
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
Absolute Maximum Ratings
(Note)
Symbol
V
CC
V
SS
T
OP
T
STG
Parameter
Voltage with respect to ground
All inputs and outputs w.r.t.
Operating temperature
Storage temperature
Rating
7
-0.6V to Vcc+1
0 to + 70 (commercial)
-40 to +85 (industrial)
-65 to +125
Unit
V
V
°C
°C
(Preliminary)
DC Electrical Characteristics
( Vcc=2.5V to 5.5V, T
Symbol
V
IH
V
IL
V
IH
V
IL
V
HYS
V
OL1
V
OL2
I
LI
I
LO
I
CC(Write)
I
CC(Read)
I
CCS
Parameter
SCL and SDA pins:
High level input voltage
SCL and SDA pins:
Low level input voltage
VCLK pin input level:
High level input voltage
VCLK pin input levels:
Low level input voltage
Hysteresis of Schmitt
inputs
Low level output voltage
Low level output voltage
Input leakage current
Output leakage current
Operating current
Operating current
standby current
AC
=0
o
C ~ +70
o
C, T
AI
= -40
o
C ~ +85
o
C)
Conditions
−
−
V
CC
≥2.7V
(Note)
V
CC
<2.7V (Note)
trigger
(Note)
I
OL
=3mA, V
CC
=2.5V (Note)
I
OL
=6mA, V
CC
=2.5V
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to V
CC
V
CC
= 5.5V, SCL=400Khz
V
CC
= 5.5V, SCL=400Khz
V
CC
= 3V, SDA=SCL= V
CC
V
CC
= 5.5V, SDA=SCL= V
CC,
VCLK=V
SS
Min.
0.7Vcc
−
2
−
0.05Vcc
−
−
-10
-10
−
−
−
−
Max.
−
0.3Vcc
−
0.2Vcc
−
0.4
0.6
10
10
3
1
30
100
Unit
V
V
V
V
V
V
V
uA
uA
mA
mA
uA
Note :
This parameter is periodically sampled and not 100% tested
Anachip Corp.
www.anachip.com.tw
3/13
Rev 0.1 Jul 2, 2003
AM24LC21B
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
AC Electrical Characteristics
Symbol
F
CLK
T
H
T
L
T
R
T
F
T
HD(ST)
T
SU(ST)
T
HD(DI)
T
SU(DI)
T
SU(STP)
T
AA
T
BUF
T
OF
T
SP
T
WR
T
VAA
T
VH
T
VL
T
VHZ
T
VPU
−
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
Start condition hold
time
Start
condition
setup time
Data input hold time
Data input setup
time
Stop
condition
setup time
Output valid from
clock
Bus free time
Output fall time from
V
IH(min)
to V
IL(max)
Input filter spike
suppression (SDA
and SCL pins)
Write cycle time
Output valid from
V
CLK
VCLK high time
VCLK low time
Mode transition time
Transmit only power
up time
Endurance
Standard Mode
Min
−
4
4.7
−
−
4
4.7
0
0.25
4
−
4.7
−
−
−
−
4
4.7
−
0
1M
Max
100
−
−
1
0.3
−
−
−
−
−
3.5
−
0.25
0.05
10
2
−
−
0.5
−
−
Vcc=4.5V~5.5V
Fast mode
Min
Max
400
−
0.6
−
1.3
−
−
−
0.6
0.6
0
0.1
0.6
−
1.3
20+0.1C
B
−
−
−
0.6
1.3
−
0
1M
0.3
0.3
−
−
−
−
−
0.9
−
0.25
0.05
10
1
−
−
0.5
−
−
cycles
Unit
Khz
us
us
us
us
us
us
us
us
us
us
us
us
us
ms
Remarks
−
−
−
(Note1)
(Note1)
After this period the first
clock pulse is generated
Only relevant for
repeated start condition
(Note 2)
−
−
(Note 2)
Time the bus must be
free before a new
transmission can start
(Note 1), C
B
≤100pF
(Note 3)
Byte or page mode
−
−
−
−
−
25
0
C, V
CC
=5V, Block
mode (Note 4)
(Preliminary)
Note 1.
Not 100% tested. C
B
=total capacitance of one bus line in pF.
Note 2.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the
falling edge of SCL to avoid unitended generation of start or stop conditions
Note 3.
The combined T
SP
and V
hys
specifications are due to new schmitt trigger inputs which provide improved noise and spike
suppression. This eliminates the need for a T
l
specification for standard operation.
Note 4.
This parameter is not tested but ensured by characterization.
Anachip Corp.
www.anachip.com.tw
4/13
Rev 0.1 Jul 2, 2003
AM24LC21B
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
Functional description
1.0 Overview
The AM24LC21B operates in two modes, the
transmit-only mode and the bi-directional mode.
There is a separate two wire protocol to support
each mode, each having a separate clock input and
sharing a common data line (SDA). The device
enters the Transmit-Only Mode upon power-up. In
this mode, the device transmits data bits on the
SDA pin in response to a clock signal on the VCLK
pin. The device will remain in this mode until a valid
high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the bi-directional mode. The
only way to switch the device back to the
transmit-only mode is to remove power from the
device.
2.1 Transmit-only mode
The device will power up in the transmit-only mode.
This mode supports a unidirectional two wire
protocol for trans-mission of the contents of the
memory array. This device requires that it be
initialized prior to valid data being sent in the
transmit-only mode (see Initialization Procedure,
SCL
T
VAA
SDA
B
IT
1(LSB)
VCLK
T
VHIGH
T
VLOW
T
VAA
N
ULL
B
IT
B
IT
8(MSB)
B
IT
7
(Preliminary)
below). In this mode, data is transmitted on the
SDA pin in 8 bit bytes, each followed by a ninth, null
bit (see Figure 2-1). The clock source for the
transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this
pin. The eight bits in each byte are transmitted most
significant bit first. Each byte within the memory
array will be output in sequence. When the last byte
in the memory array is transmitted, the output will
wrap around to the first location and continue. The
bi-directional mode clock (SCL) pin must be held
high for the device to remain in the transmit-only
mode.
2.2 Initialization procedure
After VCC has stabilized, the device will be in the
transmit-only mode. Nine clock cycles on the VCLK
pin must be given to the device for it to perform
internal synchronization. During this period, the
SDA pin will be in a high impedance state. On the
rising edge of the tenth clock cycle, the device will
output the first valid data bit which will be the most
significant bit of a byte. The device will power up at
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