V827432K24S
2.5 VOLT 32M x 72 HIGH PERFORMANCE
UNBUFFERED ECC DDR SDRAM MODULE
PRELIMINARY
CILETIV LESO M
Features
■
184 Pin Unbuffered 33,554,432 x 72 bit
Organization DDR SDRAM Modules
■
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
■
Single +2.5V (± 0.2V) Power Supply
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8196 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
DDR SDRAM Performance
Component Used
t
CK
t
AC
Clock Frequency
(max.)
Clock Access Time
CAS Latency = 2.5
Description
The V827432K24S memory module is organized
33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 9 Mosel-Vitelic
32M x 8 DDR SDRAM. The x72 modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
-6
166
-7
143
-75
133
-8
125
(PC333) (PC266A) (PC266B) (PC200)
6
7
7.5
8
Module Speed
A1
B0
B1
C0
PC1600 (100MHz @ CL2)
PC2100B (133MHz @ CL2.5)
PC2100A (133MHz @ CL2)
PC2700 (166MHz @ CL2.5)
V827432K24S Rev. 1.2 September 2002
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V827432K24S
CILETIV LESO M
Part Number Information
V
MOSELVITELIC
MANUFACTURED
8
2
74
32 K
2
4
S
X
T
G - XX
SPEED
A1 (100MHZ@CL2)
B0 (133MHZ@CL2.5)
B1 (133MHZ@CL2)
C0 (166MHZ@CL2.5)
DDR SDRAM
2.5V
WIDTH
DEPTH
184 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
STTL
4 BANKS
LEAD FINISH
G = GOLD
COMPONENT
PACKAGE, T = TSOP
COMPONENT
REV LEVEL
V827432K24S Rev. 1.2 September 2002
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V827432K24S
CILETIV LESO M
Block Diagram
DQS0
DM0
CS0
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D4
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
C S DQS
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
* Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
SDRAMs
3 SDRAMs
3 SDRAMs
3 SDRAMs
D1
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
*Clock Net Wiring
Dram1
D2
D6
R=120
Ω
Card
Edge
Cap
Dram3
Cap
Dram5
Cap
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
D7
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
D8
BA0 - BA1
A0 - A13
RAS
CAS
CKE0
WE
BA0-BA1: SDRAMs D0 - D7
V
DDSPD
SPD
D0 - D8
D0 - D8
A0-A13: SDRAMs D0 - D7 V
D D
/V
DDQ
RAS : SDRAMs D0 - D7
CAS : SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
VREF
V
SS
D0 - D8
D0 - D8
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/ CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
V827432K24S Rev.1.2 September 2002
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V827432K24S
CILETIV LESO M
Pin Configurations (Front Side/Back Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
Key key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Notes:
*
These pins are not used in this module.
Pin Names
Pin
CK1, CK1, CK2, CK2
CS0
CKE0
RAS, CAS, WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
V827432K24S Rev. 1.2 September 2002
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V827432K24S
CILETIV LESO M
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
Function Supported
Byte #
0
Hex value
A1
B0
80h
Function described
Defines # of Bytes written into serial memory at module manu-
facturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
DDR SDRAM cycle time at CAS Latency =2.5
DDR SDRAM Access time from clock at CL=2.5
DIMM configuration type(Non-parity, Parity, ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address
DDR SDRAM device attributes : Burst lengths supported
DDR SDRAM device attributes : # of banks on each DDR
SDRAM
DDR SDRAM device attributes : CAS Latency supported
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
A1
B0
B1
C0
B1
C0
128bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
256bytes
SDRAM DDR
13
10
1 Bank
72 bits
-
SSTL 2.5V
8ns
7.5ns
7ns
6ns
80h
75h
75h
08h
07h
0Dh
0Ah
01h
48h
00h
04h
70h
75h
02h
82h
08h
08h
01h
60h
70h
±0.8ns ±0.75ns ±0.75ns±0.70ns 80h
Non-parity, ECC
7.8us & Self refresh
x8
x8
t
CCD
=1CLK
2,4,8
4 banks
16
17
0Eh
04h
18
19
20
21
2,2.5
0CLK
1CLK
Differential clock /
non Registered
+/-0.2V voltage tolerance
10ns
10ns
7.5ns
7.5ns
A0h
0Ch
01h
02h
20h
22
23
24
25
26
27
DDR SDRAM device attributes : General
DDR SDRAM cycle time at CL =2
DDR SDRAM Access time from clock at CL =2
DDR SDRAM cycle time at CL =1.5
DDR SDRAM Access time from clock at CL =1.5
Minimum row precharge time (=t
RP
)
00h
A0h
75h
00h
00h
50h
50h
50h
48h
75h
75h
75h
70h
±0.8ns ±0.75ns ±0.75ns±0.70ns 80h
-
-
20ns
-
-
20ns
-
-
20ns
-
-
18ns
V827432K24S Rev.1.2 September 2002
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