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ISM74-61A8K1-1500.000

Description
LVDS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size75KB,3 Pages
ManufacturerILSI
Websitehttp://www.ilsiamerica.com
Environmental Compliance  
Download Datasheet Parametric View All

ISM74-61A8K1-1500.000 Overview

LVDS Output Clock Oscillator,

ISM74-61A8K1-1500.000 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresENABLE/DISABLE FUNCTION; TR, 7/10 INCH
maximum descent time0.6 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Nominal operating frequency1500 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeLVDS
Output load100 OHM, 10 pF
physical size5.0mm x 3.2mm x 1.4mm
longest rise time0.6 ns
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
3.2 mm x 5.0 mm Ceramic Low Noise SMD Oscillator,
LVCMOS / LVPECL / LVDS
ISM74 - Series
Product Features
Small Surface Mount Package
Low RMS Phase Jitter
Frequencies to 1500 MHz
Pb Free/ RoHS Compliant
Leadfree Processing
Applications
xDSL
Broadcast video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage
Current
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp.
Range
Storage
10 MHz to 250 MHz
10 MHz to 1500 MHz
10 MHz to 1500 MHz
VOH=90% VDD min., VOL=10 % VDD max.
VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50%VDD
50% ±5% @ 50%*
50% ±5% @ 50%*
3.0 ns max. (90%/10%)*
0.6 ns max. (80%/20%)*
0.6 ns max. (80%/20%)*
15pF
50
to VDD - 2.0 VDC
RL=100
/CL=10pF
See Table Below
3.3 VDC ± 10%, 2.5VDC ± 5%
LVCMOS = 45 mA max., LVPECL = 65 mA max. LVDS = 35 mA max.
0.5 ps typical
See Table Below
-40
C to +100
C
Bypass =0.01 uF
Recommended Pad Layout
Pin
1
2
3
4
5
6
Connection
Enable/Disable or N.C.
Enable/Disable or N.C
Ground
Output
Output or N.C.
V
DD
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Operating
Temperature
1 = 0 C to +70 C
3 = -20 C to +70 C
2 = -40 C to +85 C
ISM74–31A9H2–155.520
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Stability
(in ppm)
F =
20
A =
25
B =
50
Enable / Disable
H = Enable (Pin 1)
K = Enable (Pin 2)
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
ISM74
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI
America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
11/06/13_C
Specifications subject to change without notice
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