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P75N02LD

Description
N-Channel Logic Level Enhancement Mode Field Effect Transistor
File Size112KB,3 Pages
ManufacturerETC1
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P75N02LD Overview

N-Channel Logic Level Enhancement Mode Field Effect Transistor

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
TO-252 (D
2
PAK)
P75N02LD
D
PRODUCT SUMMARY
V
(BR)DSS
25
R
DS(ON)
5mΩ
I
D
75A
1. GATE
2. DRAIN
3. SOURCE
G
S
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
1
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy
2
Power Dissipation
L = 0.1mH
L = 0.05mH
T
C
= 25 °C
T
C
= 100 °C
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
GS
I
D
I
DM
I
AR
E
AS
E
AR
P
D
T
j
, T
stg
T
L
LIMITS
±20
75
50
170
60
140
5.6
65
38
-55 to 150
275
mJ
A
UNITS
V
W
Operating Junction & Storage Temperature Range
Lead Temperature (
1
/
16
” from case for 10 sec.)
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
Case-to-Heatsink
1
2
°C
SYMBOL
R
θJC
R
θJA
R
θCS
TYPICAL
MAXIMUM
2.3
62.5
UNITS
°C / W
0.6
Pulse width limited by maximum junction temperature.
Duty cycle
1%
ELECTRICAL CHARACTERISTICS (T
C
= 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
V
GS
= 0V, I
D
= 250µA
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 0V, V
GS
= ±20V
V
DS
= 20V, V
GS
= 0V
V
DS
= 20V, V
GS
= 0V, T
J
= 125 °C
25
1
1.5
3
±250
25
250
V
nA
µA
LIMITS
UNIT
MIN TYP MAX
1
AUG-02-2001

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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