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ISM74-63A8H2-155.520

Description
3.2 mm x 5.0 mm Ceramic Low Noise SMD Oscillator, LVCMOS / LVPECL / LVDS
File Size50KB,3 Pages
ManufacturerILSI
Websitehttp://www.ilsiamerica.com
Download Datasheet View All

ISM74-63A8H2-155.520 Overview

3.2 mm x 5.0 mm Ceramic Low Noise SMD Oscillator, LVCMOS / LVPECL / LVDS

3.2 mm x 5.0 mm Ceramic Low Noise SMD Oscillator,
LVCMOS / LVPECL / LVDS
Product Features
Small Surface Mount Package
Low RMS Phase Jitter
Frequencies to 1500 MHz
Pb Free/ RoHS Compliant
Leadfree Processing
ISM74 – Series
Applications
xDSL
Broadcast video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage
Current
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp.
Range
Storage
10 MHz to 225 MHz
10 MHz to 1500 MHz
10 MHz to 1500 MHz
VOH=90% VDD min., VOL=10 % VDD max.
VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50%VDD
50% ±5% @ 50%*
50% ±5% @ 50%*
3.0 ns max. (90%/10%)*
0.6 ns max. (80%/20%)*
0.6 ns max. (80%/20%)*
15pF
50
to VDD - 2.0 VDC
RL=100
/CL=10pF
See Table Below
3.3 VDC ± 10%, 2.5VDC ± 5%
Bypass =0.01 uF
Recommended Pad Layout
LVCMOS = 25 mA max., LVPECL = 60 mA max. LVDS = 35 mA max.
0.5 ps typical
See Table Below
-40
C to +100
C
Pin
1
2
3
4
5
6
Connection
Enable/Disable or N.C.
Enable/Disable or N.C
Ground
Output
Output or N.C.
V
DD
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Operating
Temperature
1 = 0 C to +70 C
3 = -20 C to +70 C
2 = -40 C to +85 C
ISM74–31A9H2–155.520
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Stability
(in ppm)
F =
20
A =
25
B =
50
Enable / Disable
H = Enable (Pin 1)
K = Enable (Pin 2)
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
ISM74
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI
America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
07/09/12_A
Specifications subject to change without notice
Page 1
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