STE10/100
PCI 10/100 ETHERNET CONTROLLER
WITH INTEGRATED PHY (5V)
PRODUCT PREVIEW
1.0 DESCRIPTION
The STE10/100 is a high performance PCI Fast Eth-
ernet controller with integrated physical layer inter-
face for 10BASE-T and 100BASE-TX application.
It was designed with advanced CMOS technology to
provide glueless 32-bit bus master interface for PCI
bus, boot ROM interface, CSMA/CD protocol for Fast
Ethernet, as well as the physical media interface for
100BASE-TX of IEEE802.3u and 10BASE-T of
IEEE802.3. The auto-negotiation function is also
supported for speed and duplex detection.
The STE10/100 provides both half-duplex and full-
duplex operation, as well as support for full-duplex
flow control. It provides long FIFO buffers for trans-
mission and receiving, and early interrupt mecha-
nism to enhance performance. The STE10/100 also
supports ACPI and PCI compliant power manage-
ment function.
2.0 FEATURES
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PQFP128 (14x20x2.7mm)
ORDERING NUMBER: STE10/100
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PCI bus interface Rev. 2.2 compliant
ACPI and PCI power management standard
compliant
Support PC99 wake on LAN
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2.2 FIFO
s
Provides independent transmission and
receiving FIFOs, each 2k bytes long
Pre-fetches up to two transmit packets to
minimize inter frame gap (IFG) to 0.96us
Retransmits collided packet without reload from
host memory within 64 bytes.
Automatically retransmits FIFO under-run
packet with maximum drain threshold until 3rd
time retry failure without influencing the
registers and transmit threshold of next packet.
2.1 Industry standard
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IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
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s
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Figure 1. STE10/100Block Diagram
DMA
MII
Controller
Flow
Control
Manchester
Encoder
10 TX
Filter
Transmitter
125Mhz
25Mhz
4B/5B
Scrambler
Auto
Negotiation
PCI Controller
Tx FiFo
Rx FiFo
5B/4B
TX Freq.
Synth.
Adaptive
Equalization
20Mhz
Descrambler
100 clock
Recovery
Manchester
Decoder
MAC SubLaye
MII Controller
BaseLine
Restore
+
_
10 clock
Recovery
Link
Polarity
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STE10/100
2.3 PCI I/F
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Provides 32-bit PCI bus master data transfer
Supports PCI clock with frequency from 0Hz to 33MHz
Supports network operation with PCI system clock from 20MHz to 33MHz
Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the
performance
Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU
utilization
As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write,
memory-write-and-invalidate command
Supports big or little endian byte ordering
s
s
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2.4 EEPROM/Boot ROM I/F
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s
s
s
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Provides writeable Flash ROM and EPROM as boot ROM, up to 128kB
Provides PCI to access boot ROM by byte, word, or double word
Re-writes Flash boot ROM through I/O port by programming register
Provides serial interface for read/write 93C46 EEPROM
Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency , and
Minimum-Grand from the 64 byte contents of 93C46 after PCI reset de-asserted
2.5 MAC/Physical
s
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s
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s
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Integrates the complete set of Physical layer 100BASE-TX and 10BASE-T functions
Provides Full-duplex operation in both 100Mbps and 10Mbps modes
Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps
Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
Provides transmit wave-shaper, receive filters, and adaptive equalizer
Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic
Built-in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
Supports external transmit transformer with 1.414:1 turn ratio
Supports external receive transformer with 1:1 turn ratio
2.6 LED Display
s
Provides 2 LED display modes:
3 LED displays for
100Mbps (on) or 10Mbps (off)
Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free)
FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
4 LED displays for
100 Link (On when 100M link ok)
10 Link (On when 10M link ok)
Activity (Blinks at 10Hz when receiving or transmitting)
FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
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STE10/100
2.7 Miscellaneous
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ACPI and PCI compliant power management functions offer significant power-savings performance
Provides general purpose timers
128-pin QFP package
Figure 2. System Diagram of the STE10/100
Serial
EEPROM
Boot ROM
PCI
Interface
STE10/100
Xfmr
Medium
LEDs
25 MHz
Crystal
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STE10/100
3.0 PIN ASSIGNEMENT DIAGRAM
Figure 3. Pin Connection
V
DD
-PCI
V
DD
-PCI
PCI-CLK
V
SS
-PCI
V
SS
-PCI
AV
SS
T
AV
DD
R
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
V
DD
-PCI
AD-8
C-BEB0
AD-7
AD-6
V
SS
-PCI
AD-5
AD-4
V
DD
-PCI
V
SS
-IR
BrA-4
BrA-5
BrA6
V
SS
-IR
V
SS
-PCI
BrA -0
BrA-1
BrA-2
BrA-3
VDD-IR
BrA-7
AD-2
AD-1
AD-0
AD-3
N.C.
V
DD
-IR
V
SS
-IR
AV
SS
R
AV
DD
T
AD-30
AD-26
AD-27
AD-28
AD-29
AD-31
PME#
REQ#
GNT#
INTA#
RST#
TX+
RX+
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
AD-25
AD-24
C-BEB3
IDSEL
V
SS
-PCI
AD-23
AD-22
V
DD
-PCI
AD-21
AD-20
V
SS
-PCI
AD-19
AD-18
V
DD
-PCI
AD-17
AD-16
C-BEB2
FRAME#
V
SS
-PCI
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
V
DD
-PCI
C-BEB1
AD-15
AD-14
V
SS
-PCI
AD-13
AD-12
AD-11
AD-10
V
SS
-PCI
AD-9
V
DD
-IR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AV
SS
I
I
REF
AV
DD
I
AV
DD
X
X1
X2
AVSSX
AV
DD
REC
AV
SS
REC
V
SS
-IR
LED M1/M2
LED M1/M2
LED M1/M2
V
CC
-detect
V
CC
-detect
BrA-16/LED M2
BrA-15
V
DD
-IR
BrA-14
BrA-13
BrA-12
BrA-11
BrA-10
BrWE#
BrOE#
BrCS#
EECS
V
SS
-IR
BrD-7/ECK
BrD-6/EDI
BrD-5/EDO
BrD-4
BrD-3
BrD-2
BrD-1
BrD-0
BrA-9
BrA-8
RX-
TX-
D99TL443
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STE10/100
4.0 4. PIN DESCRIPTION
Table 1. Pin Description
Pin No.
Name
Type
Description
PCI bus Interface
113
114
INTA#
RST#
O/D
I
PCI interrupt request. STE10/100 asserts this signal when one of the interrupt
event is set.
PCI Reset signal to initialize the STE10/100. The RST signal should be asserted
for at least 100µs to ensure that the STE10/100 completes initialization. During
the reset period, all the output pins of STE10/100 will be placed in a high-
impedance state and all the O/D pins are floated.
PCI clock input to STE10/100 for PCI Bus functions. The Bus signals are
synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a
frequency in the range between 20MHz and 33MHz to ensure proper network
operation
PCI Bus Granted. This signal indicates that the STE10/100 has been granted
ownership of the PCI Bus as a result of a Bus Request.
PCI Bus Request. STE10/100 asserts this line when it needs access to the PCI
Bus.
The Power Management Event signal is an open drain, active low signal. The
STE10/100 will assert PME# to indicate that a power management event has
occurred.
When WOL (bit 18 of CSR18) is set, the STE10/100 is placed in Wake On LAN
mode. While in this mode, the STE10/100 will activate the PME# signal upon
receipt of a Magic Packet frame from the network.
In the Wake On LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-WAKE
signal follows HP’s protocol; otherwise, it is IBM protocol.
Multiplexed PCI Bus address/data pins
116
PCI-CLK
I
117
118
119
GNT#
REQ#
PME#
I
O
O
OD
120,121
123,124
126,127
1,2
6,7
9,10
12,13
15,16
29,30
32~35
37
41
43,44
46,47
49,50
52,53
3
17
28
42
4
18
20
AD-31,30
AD-29,28
AD-27,26
AD-25,24
AD-23,22
AD-21,20
AD-19,18
AD-17,16
AD-15,14
AD-13~10
AD-9
AD-8
AD-7, 6
AD-5,4
AD-3,2
AD-1,0
C-BEB3
C-BEB2
C-BEB1
C-BEB0
IDSEL
FRAME#
IRDY#
I/O
I/O
Bus command and byte enable
I
I/O
I/O
Initialization Device Select. This signal is asserted when the host issues
configuration cycles to the STE10/100.
Asserted by PCI Bus master during bus tenure
Master device is ready to begin data transaction
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