W.A.R.P.2.0
8-BIT FUZZY CO-PROCESSOR
PRELIMINARY DATA
Digital Fuzzy Co-processor 8-bit I/O
High Speed Rules Processing
4 Input, 2 Output, 32 Rules in 33.1µs
Up to 256 Rules (4 Antecedents,1 Consequent)
Up to 8 Input Configurable Variables
Up to 16 Membership Functions for an Input
Variable
Antecedent Membership Functions with
Triangular and Trapezoidal Shape
Up to 4 Output Variables
Up to 256 Membership Functions for all
Consequents
Singleton Consequent Membership Functions
Defuzzification on chip
Maximum Clock Frequency 40MHz
A/D Start Convertion Pulse presettable
Direct Interface to all popular microprocessor
Handshaking Signal Polarity presettable
Operates ”STAND ALONE” (without
µP)
if
desired
Standard +5V Supply Voltage
Software Tools and Emulators Availability
Pin number: 52
68-lead Plastic Leaded Chip Carrier package.
Figure 2. Simplified Block Diagram.
8
Input Port
with
HANDSHAKE
ALPHA
CALCULATOR
INFERENCE
UNIT
8
DEFUZZIFIER
Ouput Port
with
HANDSHAKE
PLCC68
Figure 1. Logic Diagram.
MCLK VSS
8
VDD WAIT
12
I0-I7
3
O0-O11
2
SIS0-SIS2
LASTIN
OE
AUTO
RD
OC0-OC1
W.A.R. P.
2.0
DS
ENDOFL
READY
ERR OFL PRESET BUSY
INTERNAL BUS
ANTECE DENT
MEMORY
P ROGRAM &
CONSE QUENT
MEMORY
P ROGRAMMABLEA/D
OUTPUT PULSE
March 1996
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/28
W.A.R.P.2.0
Figure 3. Pin Connections
nc
nc
I7
I6
I5
I4
I3
I2
VSS
I1
I0
WAIT
SIS0
SIS1
SIS2
nc
nc
9
8
7
6
5 4 3
2
1 68 67 66 65 64 63 62 61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS
VDD
MCLK
PRESET
OFL
AUTO
LASTIN
OE
RD
TEST
DS
ENDOFL
ERR
BUSY
READY
VSS
VDD
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
W.A.R.P. 2.0
nc
nc
nc
VDD
VSS
O0
O1
O2
O3
O4
O5
O6
VDD
VSS
nc
nc
nc
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Note: nc = Not Connected.
GENERAL DESCRIPTION
W.A.R.P.2.0 is a member of the W.A.R.P. family of
fuzzy microprocessors, completely developed and
produced by SGS-THOMSON Microelectronics us-
ing the high performance, reliable HCMOS4T
(O.7µm) process.
W.A.R.P.2.0 can be used both as a Fuzzy Co-proc-
essor or as a stand-alone microcontroller. In the
former case, it can work together with standard
micros which shall perform normal control tasks
while W.A.R.P.2.0 will be indipendentlyresponsible
for all the fuzzy related computing.
W.A.R.P.2.0 core includes the fuzzifier (ALPHA
calculator), the inference unit, and the defuzzifier.
The I/O capabilities demanded by microprocessor
applications are fulfilled by W.A.R.P.2.0 with 8 Input
and 4 Output lines which can be supported by
handshaking signals.
The capability of preset the polarity of the hand-
shaking signals simplifies the interface with the
host processor.
An internal Start Conversion pulse is provided to
allow simple use for waveform generation which
can be directly applied to drive an A/D converter.
The output 3-STATE buffer can be temporarily
frozen in order to synchronize W.A.R.P.2.0 with
slower devices.
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nc
nc
nc
VSS
VDD
OC1
OC0
O11
O10
O9
O8
O7
VSS
VDD
nc
nc
nc
Running W.A.R.P.2.0 involves a downloading
phase and an On-Line phase. The downloading
phase allows the setting of the processor, in terms
of I/O number, universe of discourse, Membership
Functions (MFs) and rules. During this phase
W.A.R.P.2.0 prepares its internal memories for the
On-Line elaboration phase and loads the micro-
code in its program memory. This microcode, which
drives the On-Line phase, is generated by the
Compiler (see FUZZYSTUDIO™ 2.0 User Man-
ual). After that W.A.R.P.2.0 is ready to run (On-Line
phase) processing inputs and producing the re-
lated outputs according to the configuration loaded
in the downloading phase. It is also possible to
provide the processor with inputs in any order by
specifying their identification numbers.
Two basic memories are available in W.A.R.P.2.0 :
the Antecedent Memory (AM) and the Pro-
gram/Consequent Memory (PCM). The antece-
dent MFs, portrayed by a resolution of 2
8
elements,
are stored in the AM (256 bytes). W.A.R.P.2.0
exploits a SGS-THOMSON patented strategy to
store the MFs in the AM.
The information about Rules and Consequent MFs
are stored in the PCM (1.4 Kbyte).
FUZZYSTUDIO™ 2.0 is a powerful development
environment consisting of board and software al-
lows an easy configuration and use of W.A.R.P.2.0.
W.A.R.P.2.0
Table 1. Pin Description
Pin Assignment
11,26,31,40,48,57
1,10,25,30,39,47,56
19
12
13
15
65
64
63
67
68
2
3
4
5
6
7
14
18
16
17
66
24
21
23
20
22
33
32
55
54
53
52
51
50
49
38
37
36
35
34
Name
VDD
VSS
TEST
MCLK
PRESET
AUTO
SIS0
SIS1
SIS2
I0
I1
I2
I3
I4
I5
I6
I7
OFL
RD
LASTIN
OE
WAIT
READY
ENDOFL
BUSY
DS
ERR
OC0
OC1
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
Pins Type
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function
Power Supply
Ground
Testing (It must be connected to VSS)
Master Clock (up to 40 MHz)
Preset
Auto/Manual-Boot
Auto-Boot Speed (Ext. Memory Support AccessTime) /
Input Selection bit 0
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 1
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 2
Data Input bit 0
Data Input bit 1
Data Input bit 2
Data Input bit 3
Data Input bit 4
Data Input bit 5
Data Input bit 6
Data Input bit 7
Off-Line/On-Line Switch
Handshaking Read Ready
Last Input (Start Elaboration) bit
Output Enable/3-STATE bit
Temporary Output Processing Stop
Handshaking Output Signal
Offline Phase (external memory downloading) End
Elaboration Phase Indicator
Data Strobe (Output Ready Signal)
Error Flag
Output Identifier bit 0
Output Identifier bit 1
External Memory Address/Defuzzified Output bit 0
External Memory Address/Defuzzified Output bit 1
External Memory Address/Defuzzified Output bit 2
External Memory Address/Defuzzified Output bit 3
External Memory Address/Defuzzified Output bit 4
External Memory Address/Defuzzified Output bit 5
External Memory Address/Defuzzified Output bit 6
External Memory Address/Defuzzified Output bit 7
External Memory Address bit 8 /
Next Input Progressive Number bit 0
External Memory Address bit 9 /
Next Input Progressive Number bit 1
External Memory Address bit 10 /
Next Input Progressive Number bit 2
External Memory Address bit 11 /
Start Conversion for the external A/D
3/28
W.A.R.P.2.0
PIN DESCRIPTION
Signals READY, RD, WAIT, DS, BUSY, LASTIN
and O11 ( external A/D Start Conversion) have
programmable polarity, see table 6 for default
values.
V
DD
, V
SS
.
Power is supplied to W.A.R.P. using
these pins. V
DD
is the power connection and V
SS
is
the ground connection; multi-connections are nec-
essary.
MCLK.
Master Clock
(Input): This is the input
master clock whose frequency can reach up to
40MHz (MAX).
During the Off-Line phase with AUTO
High,
the
MCLK is internally divided to utilize boot memories
working with a slower frequency.The access speed
is presettable by means of SIS0-SIS2 pins.
PRESET.
Preset
(Input, active Low)
:
This is the
restart pin of W.A.R.P.. It is possible to restart the
work during the computation (On-Line phase) or
before the writing of internal memories (Off-Line
phase). In both cases it must be put
Low
at least
for a clock period. After PRESET
Low
the proces-
sor remains in the reset status 3 MCLK pulses.
AUTO.
Auto-Boot:
(Input, active High): During the
Off-Line phase AUTO
High
enables the automatic
boot of W.A.R.P.2.0 whereas AUTO
Low
validates
the manual downloading. The manual boot has to
be performed using the handshaking signals
RD/READY.
During the On-Line phase AUTO
High
disables
the generation of the Start A/D conversion (O11)
signal.
SIS0-SIS2.
Speed & Input Selection
(Inputs): Dur-
ing the Off-Line phase with AUTO
High
(Auto-Boot)
SIS bus allows to choose the speed of downloading
from the external memory which contains the start-
up configuration of W.A.R.P.2.0. In that case (Auto-
Boot) MCLK is internally divided to provide a slower
sinchronization signal which is automatically used
as RD for the reading of the external memory. Table
2 shows how to preset the frequency of this syn-
chronization signal.
During the On-Line phase in Slave mode (see
Register Bench description, Tab.5) SIS bus allows
to provide W.A.R.P.2.0 with inputs in any order by
specifying their identification number. The input
and its identification number (SIS0-SIS2) will be
acquired at the next active RD so they must be
already stable when RD is given.
Table 2. Downloading Speed
SIS0
Low
High
SIS1
Low
Low
SIS2
Low
Low
Internal Synchronization
Signal Frequency
MCLK/32
MCLK/16
I0-I7.
Input bus
(Input): During the Off-Line phase
these 8 data input pins accept addresses and data
from the external boot memory containing
W.A.R.P.2.0 configuration. This start-up memory
(which can be a ZERO-POWER, the host proces-
sor memory, an EPROM, a Flash, the PC Memory,
etc.) contains the fuzzy project built by means of
FUZZYSTUDIO™ 2.0.
In On-Linemode this bus carries the input variables
according to the prefixed order.
OFL.
Offline
(Input, active High): When this pin is
High,
the chip is enabled to load data in the internal
RAMs (Off-Line phase). It must be
Low
when the
fuzzy controller is waiting for input values and
during the processing phase (On-Line phase).
When OFL changes its status the processor re-
mains presetted for 3 clock pulses.
LASTIN.
Last Input
(Input, default active High):
During the On-Line phase in slave mode (see
Register Bench description, table 5) LASTIN
High
indicates no other inputs have to be provided so
W.A.R.P.2.0 can start the processing phase.
W.A.R.P.2.0 inputs are those in the input interface
so if some variables do not need to be acquired
again (because they change slower than others)
they remain stored and no extra time is required to
acquire them again.
OE.
Output Enable
(Input, active Low): OE
Low
enables O0-011output bus or (if
High)
put it in
3-STATE.
WAIT.
Wait
(Input, default active High): This pin
High
stops the output processing. When WAIT is
enabled W.A.R.P.2.0 finishes to compute the cur-
rent output variable but it does not give it on the
output bus until WAIT becomes
Low.
This signal
allows to synchronize W.A.R.P.2.0 with slower de-
vices.
RD.
Read
(Input, default active High): Both in
Off-Line and in On-Line mode RD indicates data
are ready to be acquired from the input bus I0-I7.
READY.
Ready
(Output, default active High): Both
in Off-Line and in On-Line mode RD indicates data
have been acquired from the input bus I0-I7 and
are now stored in W.A.R.P.2.0 internal registers.
ENDOFL.
End of Off-Line phase
(Output, active
High): This pin indicates the end of the download-
ing phase (Off-Line) so the content of the boot
memory is already stored in W.A.R.P.2.0 internal
memories. After ENDOFL is active the user can put
OFL
Low
so the On-Line phase can start.
BUSY.
Busy Signal
(Output, default active High):
When the elaboration phase is running this pin is
active. When W.A.R.P.2.0 finishes to compute the
last output variable, it puts BUSY
Low
and waits
for new inputs.
4/28
W.A.R.P.2.0
DS.
Data Strobe
(Output, default active High): The
strobe pin enables the user to utilize the output.
When this pin is
High
it indicates that a new output
variable has been calculated and it is ready on the
output bus (O0-O7). This signal synchronizes the
external devices and in particular the interfaces
with the controlled processes (On-Line mode).
ERR.
Error
(Output, active Low): When this pin is
active, W.A.R.P.2.0 has incurred in an internal error
condition.
OC0-OC1.
Output Counter
(Output): This 2 bit
output bus provides the output variables with a
progressive number during the On-Line phase. As
a consequence it is possible to know to which
variable correspond the data that are on the output
data bus (O0-O7). The dimension of OC bus is
connected with the maximum number of output
variables (4).
O0-O11.
Output Bus
(Output): In the Off-Line
phase these pins provide the addresses (12 bit) for
its internal memories and send those addresses to
the external memory support where data to load are
located. These addresses sent on O0-O11 bus
allow to identify the data that have to be loaded in
W.A.R.P.2.0 internal memories.
In the On-Line phase O0-O7 carrie out the output
values. When the DS is
High,
one output variable
can be read by external devices. The resolution
of output variables is 256 points (8 bit). If there is
more than one output, the output variables are
calculated one by one and they are provided in
the sequence stabilized during the editing phase
(see FUZZYSTUDIO™ 2.0 User Manual).
In On-Line mode O8-O10 provide the progressive
number of the next variable to be acquired. These
pins can be used to select the next input to provide
on I0-I7 bus.
Still in on-line mode O11 allows to provide a preset-
table signal which can be used as Start-Conversion
for an A/D converter after (about 400 ns) OFL or
BUSY fall.
5/28
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