Intel
®
LXT974/LXT975 Fast Ethernet
10/100 Mbps Quad Transceivers
Datasheet
The Intel
®
LXT974 and LXT975 Fast Ethernet 10/100 Mbps Quad Transceivers (called
hereafter the LXT974/975 Transceiver) are four-port PHY Fast Ethernet Transceivers, which
support IEEE 802.3 physical layer applications at both 10 Mbps and 100 Mbps. They provide
all of the active circuitry to interface four 802.3 Media Independent Interface (MII) compliant
controllers to 10BASE-T and/or 100BASE-TX media.
This data sheet applies to all versions of the LXT974 and LXT975 products including
LXT974A, LXT974B, LXT975A, and LXT975B. As a result of product changes, Revision 4
parts are labeled LXT974B and LXT975B. Revision 3 parts are labeled LXT974A and
LXT975A. The differences in these product revisions are described in the LXT974/975
Specification Update.
All four ports on the LXT974 provide a combination twisted-pair (TP) or pseudo-ECL (PECL)
interface for a 10/100BASE-TX or 100BASE-FX connection.
The LXT975 is pin compatible with the LXT974 except for the network ports. The LXT975 is
optimized for dual-high stacked RJ-45 modular applications and provides a twisted-pair
interface on every port, but the PECL interface on only two.
The LXT974/975 provides three separate LED drivers for each of the four PHY ports and a
serial LED interface. In addition to standard Ethernet, each chip supports full- duplex operation
at 10 Mbps and 100 Mbps. The LXT974/975 requires only a single 5V power supply. The MII
may be operated independently with either a 3.3V or 5V supply.
Applications
■
10BASE-T, 10/100-TX, or 100BASE-
FX Switches and multi-port NICs.
■
LXT975 optimized for dual-high stacked
modular RJ-45 applications.
Product Features
■
■
■
■
■
■
Four independent IEEE 802.3-
compliant 10BASE-T or 100BASE-
TX ports in a single chip.
100BASE-FX fiber-optic capable.
Standard CSMA/CD or full-duplex
operation.
Supports auto-negotiation and legacy
systems without auto-negotiation
capability.
Baseline wander correction.
100BASE-TX line performance over
130 meters.
■
■
■
■
■
Configurable LED drivers and serial LED output.
Configurable through MII serial port or via
external control pins.
Available in 160-pin PQFP with heat spreader.
Commercial temperature range (0-70
o
C
ambient).
Part numbers:
— Intel® HBLXT974BHC Transceiver
— Intel® WBLXT974BHC Transceiver (RoHS
Compiant)
— Intel® HBLXT975BHC Transceiver
— Intel® WBLXT975BHC Transceiver (RoHS
Compliant)
Order Number: 249274-002
17-Jan-2005
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The Intel
®
LXT974/LXT975 Fast Ethernet 10/100 Mbps Quad Transceivers may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
........................................................................................... 19
2.1
2.2
Introduction.......................................................................................................... 19
Network Media / Protocol Support.......................................................................20
2.2.1 10/100 Mbps Network Interface ............................................................. 20
2.2.1.1 Twisted-Pair Interface ............................................................... 20
2.2.1.2 Fiber Interface ........................................................................... 21
2.2.2 MII Interface ........................................................................................... 21
2.2.2.1 MII Data Interface ...................................................................... 21
2.2.2.2 MII Management Interface ........................................................ 24
2.2.3 Hardware Control Interface .................................................................... 25
Initialization.......................................................................................................... 27
2.3.1 MDIO Control Mode ............................................................................... 27
2.3.2 Manual Control Mode ............................................................................. 27
2.3.3 Link Configuration .................................................................................. 28
Auto-Negotiation.................................................................................................. 29
2.4.1 Parallel Detection ................................................................................... 29
2.4.2 Controlling Auto-Negotiation ..................................................................29
2.4.3 Monitoring Auto-Negotiation ................................................................... 29
100 Mbps Operation ............................................................................................30
2.5.1 100BASE-X MII Operations.................................................................... 30
2.5.2 100BASE-X Network Operations ...........................................................30
2.5.3 100BASE-X Protocol Sublayer Operations ............................................ 33
2.5.4 PCS Sublayer......................................................................................... 33
2.5.4.1 Preamble Handling .................................................................... 33
2.5.4.2 Data Errors ................................................................................ 34
2.5.4.3 Collision Indication .................................................................... 34
2.5.5 PMA Sublayer ........................................................................................ 35
2.5.5.1 Link ............................................................................................35
2.5.5.2 Link Failure Override ................................................................. 35
2.5.5.3 Carrier Sense (CRS) ................................................................. 35
2.5.6 Twisted-Pair PMD Sublayer ................................................................... 35
2.5.6.1 Scrambler/Descrambler (100TX Only) ...................................... 35
2.5.6.2 Baseline Wander Correction ..................................................... 36
2.5.6.3 Polarity Correction ..................................................................... 36
2.5.7 Fiber PMD Sublayer ............................................................................... 36
10 Mbps Operation.............................................................................................. 36
2.6.1 10BASE-T MII Operation........................................................................ 36
2.6.2 10BASE-T Network Operations.............................................................. 36
2.6.2.1 Preamble Handling .................................................................... 37
2.6.2.2 Link Test .................................................................................... 37
2.6.2.3 Link Failure ................................................................................ 37
2.6.2.4 SQE (Heartbeat)........................................................................ 37
2.6.2.5 Jabber ....................................................................................... 37
LED Functions..................................................................................................... 37
2.7.1 Serial LED Output .................................................................................. 38
2.3
2.4
2.5
2.6
2.7
Datasheet
3
LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
2.8
Per Port LEDs ........................................................................................ 38
2.7.2.1 LEDn_0 ..................................................................................... 38
2.7.2.2 LEDn_1 ..................................................................................... 38
2.7.2.3 LEDn_2 ..................................................................................... 38
Operating Requirements ..................................................................................... 39
2.8.1 Power Requirements.............................................................................. 39
2.8.1.1 MII Power Requirements........................................................... 39
2.8.1.2 Low-Voltage Fault Detect .......................................................... 39
2.8.1.3 Power Down Mode .................................................................... 39
2.8.2 Clock Requirements ............................................................................... 39
2.7.2
3.0
Application Information
......................................................................................... 40
3.1
Design Recommendations .................................................................................. 40
3.1.1 General Design Guidelines .................................................................... 40
3.1.2 Power Supply Filtering ........................................................................... 40
3.1.2.1 Ground Noise ............................................................................ 41
3.1.3 Power and Ground Plane Layout Considerations .................................. 41
3.1.3.1 Chassis Ground......................................................................... 41
3.1.4 MII Terminations .................................................................................... 41
3.1.5 The RBIAS Pin ....................................................................................... 42
3.1.6 The Twisted-Pair Interface ..................................................................... 42
3.1.7 The Fiber Interface ................................................................................. 42
Magnetics Information ......................................................................................... 43
3.2.1 Magnetics With Improved Return Loss Performance............................. 43
Twisted-Pair/ RJ-45 Interface.............................................................................. 44
3.2
3.3
4.0
5.0
6.0
7.0
Test Specifications
.................................................................................................. 50
Register Definitions
................................................................................................ 63
Package Specification
............................................................................................ 73
6.1
Top Label Markings............................................................................................. 74
Ordering Information
.............................................................................................. 75
4
Datasheet
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Figures
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Intel
®
LXT974/975 Transceiver Block Diagram..................................................... 9
LXT974 Pin Assignments ................................................................................... 10
LXT975 Pin Assignments ................................................................................... 12
LXT974 Switch Application ................................................................................. 19
LXT975 Switch Application ................................................................................. 20
MII Data Interface ............................................................................................... 22
Loopback Paths .................................................................................................. 24
Management Interface - Read Frame Structure ................................................. 25
Management Interface - Write Frame Structure ................................................. 25
MDIO Interrupt Signaling .................................................................................... 25
Hardware Interface Mode Selection ................................................................... 28
LXT974/975 Auto-Negotiation Operation ...........................................................30
100BASE-TX Data Flow .....................................................................................31
100BASE-TX Frame Structure ........................................................................... 31
LXT974/975 Protocol Sublayers .........................................................................33
100BASE-TX Reception with No Errors ............................................................. 34
100BASE-TX Reception with Invalid Symbol ..................................................... 34
100BASE-TX Transmission with No Errors ........................................................ 34
100BASE-TX Transmission with Collision .......................................................... 34
Typical LXT974 Twisted-Pair Single RJ-45 Modular Application ....................... 44
Typical LXT975 Twisted-Pair Stacked RJ-45 Modular Application .................... 45
LXT974/975 Power and Ground Connections ....................................................46
Typical Twisted-Pair Interface and Supply Filtering ........................................... 47
Typical Fiber Interface ........................................................................................ 48
Typical MII Interface ........................................................................................... 49
MII - 100BASE-TX Receive Timing .................................................................... 53
MII - 100BASE-TX Transmit Timing ................................................................... 54
MII - 100BASE-FX Receive Timing .................................................................... 55
MII - 100BASE-FX Transmit Timing ................................................................... 56
MII - 10BASE-T Receive Timing ........................................................................ 57
MII - 10BASE-T Transmit Timing .......................................................................58
10BASE-T SQE (Heartbeat) Timing ................................................................... 58
10BASE-T Jab and Unjab Timing ...................................................................... 59
Auto Negotiation and Fast Link Pulse Timing ....................................................60
Fast Link Pulse Timing ....................................................................................... 60
MDIO Timing when Sourced by STA ................................................................. 61
MDIO Timing When Sourced by PHY ................................................................ 61
Power Down Timing ........................................................................................... 62
Serial LED Timing .............................................................................................. 62
PHY Identifier Bit Mapping .................................................................................. 66
LXT974/975 Package Specification ................................................................... 73
Sample HQFP Package – Intel
®
HBLXT97xBHC Transceiver............................ 74
Sample Pb-Free (RoHS-Compliant) HQFP Package –
Intel
®
WBLXT97xBHC Transceiver ..................................................................... 74
Ordering Information Matrix – Sample ................................................................ 76
Datasheet
5
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