CHV1812N250821KXT-LF datasheet, PDF

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CHV1812N250821KXT-LF: DescriptionCeramic Capacitor, Multilayer, Ceramic, 250V, 10% +Tol, 10% -Tol, X7R, 15% TC, 0.00082uF, Surface Mount, 1812, CHIP, ROHS COMPLIANT; CategoryPassive components capacitor; File Size2MB，8 Pages; ManufacturerCal-Chip Electronics; Environmental Compliance

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CHV1812N250821KXT-LF Overview

Ceramic Capacitor, Multilayer, Ceramic, 250V, 10% +Tol, 10% -Tol, X7R, 15% TC, 0.00082uF, Surface Mount, 1812, CHIP, ROHS COMPLIANT

CHV1812N250821KXT-LF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Cal-Chip Electronics
package instruction	, 1812
Reach Compliance Code	compliant
ECCN code	EAR99
capacitance	0.00082 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	1.8 mm
length	4.5 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	TR, EMBOSSED PLASTIC, 7 INCH
positive tolerance	10%
Rated (DC) voltage (URdc)	250 V
size code	1812
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
width	3.2 mm

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Cal-Chip

Introduction

Electronics, Incorporated

Handling

CHV S

ERIES

High Voltage Ceramic Chip Capacitors

Cal-Chip Electronics, Incorporated operates a policy of continuous

development for its ranges of Multilayer Ceramic Capacitors. Our

unique construction process ensures excellent volumetric efficiency

and stability of capacitance with temperature.

High Voltage Chip MLC’s have extended values in the 500V series to

those previously offered, together with

voltage ranges up to 10kV.

Ceramics are dense, hard, brittle and abrasive materials. They are

liable to suffer mechanical damage in the form of chips or cracks, if

improperly handled.

MLC’s should never be handled with metallic instruments.

IELECTRIC

HARACTERISTICS

Dielectric classification:

Rated temperature range:

Maximum capacitance change

over temperature range

Tangent of loss angle (tan

δ)

COG / NPO

X7R

Y5V & Z5U

Ultra Stable

-55°C to +125°C

0±30ppm/°C

Cr>50pF≤0.0015

Cr≤50pF=0.0015 (15+0.7)

100GΩ or

1000s

<10pF ±0.25, ±0.5pF

≥10pF

±1, ±2, ±5, ±10%

1.5 x rated volts

55/125/56

Zero

Stable

-55°C to +125°C

±15%

≤0.025

General Purpose

+10°C to +85°C

+22 to -56%

≤0.030

Insulation resistance (Ri)

Time Constant (Ri X Cr)

(whichever is less)

Capacitance tolerance

Proof

Voltage

500V

≥1kV

100GΩ or

1000s

+5%, ±10%, ±20%

1.5 x rated volts

1.25 x rated volts

55/125/56

1% per time decade

10GΩ or

100s

±20%, -20+80%

1.5 x rated volts

25/085/56

6% per time decade

Climatic category (IEC)

Aging characteristic (Typ.)

URFACE

OUNT

HIP

APACITORS

Ordering Information

Example:

Chip Type

Type No/Size Ref

Termination Options

F=Silver Palladium

N=Nickel Barrier

A=High Leach Resistant Silver Palladium

Voltage d.c.

500=500V

1k0=1kV

2k0=2kV

CHV

3640

1k0

103

- LF

Optional RoHS

Designator

Packaging

T=178mm(7" reel)

Dielectric Code

C=COG, X=X7R, Z=Z5U,

Y=Y5V

Capacitance Tolerance

Code

F=1%

G=2%

J=5%

K=10%

M=20%

Z=20-80%

3k0=3kV

4k0=4kV

5k0=5kV

250=250V

10k0=10kV

Capacitance Code

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