EVB71121
300 to 930MHz Receiver
Evaluation Board Description
Features
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Dual RF input for antenna space and frequency diversity, LNA cascading or differential feeding
Fully integrated PLL-based synthesizer
2
nd
mixer with image rejection
Reception of ASK or FSK modulated signals
Wide operating voltage and temperature ranges
Very low standby current consumption
Low operating current consumption
Internal IF filter
Internal FSK demodulator
Average or peak detection data slicer mode
RSSI output with high dynamic range for RF level indication
Output noise cancellation filter
MCU clock output
High over-all frequency accuracy
Ordering Information
Part No. (see paragraph 4)
EVB71121-315-C
EVB71121-433-C
Note 1:
Peak detection mode is default population.
Application Examples
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General digital and analog RF receivers
at 300 to 930MHz
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Tire pressure monitoring systems (TPMS)
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Remote keyless entry (RKE)
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Low power telemetry systems
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Alarm and security systems
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Active RFID tags
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Remote controls
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Garage door openers
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Home and building automation
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EVB71121-868-C
EVB71121-915-C
General Description
The MLX71121 is a multi-band, single-channel RF receiver based on a double-conversion super-heterodyne
architecture. It can receive FSK and ASK modulated signals. The IC is designed for general purpose
applications for example in the European bands at 433MHz and 868MHz or for similar applications in North
America or Asia, e.g. at 315MHz or 915MHz.
The receiver’s extended temperature and supply voltage ranges make the device a perfect fit for automotive
or similar applications where harsh environmental conditions are expected.
39012 71121 01
Rev. 003
Page 1 of 18
EVB Description
Jan/08
EVB71121
300 to 930MHz Receiver
Evaluation Board Description
Document Content
1
Theory of Operation ...................................................................................................3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
General............................................................................................................................. 3
Technical Data Overview.................................................................................................. 3
Block Diagram .................................................................................................................. 4
Operating Modes .............................................................................................................. 5
Frequency Range ............................................................................................................. 5
LNA Selection................................................................................................................... 5
Demodulation Selection.................................................................................................... 5
Data Slicer ........................................................................................................................ 5
2
Frequency Planning ...................................................................................................6
2.1
2.2
2.3
Calculation of Frequency Settings.................................................................................... 7
Standard Frequency Plans ............................................................................................... 8
433/868MHz Frequency Diversity .................................................................................... 8
3
Dual-Channel Application Circuits for FSK & ASK Reception ...............................9
3.1
3.1.1
Peak Detector Data Slicer ................................................................................................ 9
Component Arrangement Top Side (Peak Detection Data Slicer) ............................................ 10
3.2
3.2.1
Averaging Data Slicer Configured for-Bi Phase Codes .................................................. 11
Component Arrangement Top Side (Averaging Data Slicer) .................................................... 12
3.3
3.4
Component List for Antenna Space Diversity ................................................................. 13
PCB Layouts for Antenna Space Diversity ..................................................................... 14
4
5
Board Variants..........................................................................................................14
Package Description ................................................................................................15
5.1
Soldering Information ..................................................................................................... 15
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Reliability Information .............................................................................................16
ESD Precautions ......................................................................................................16
Disclaimer .................................................................................................................18
39012 71121 01
Rev. 003
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EVB Description
Jan/08
EVB71121
300 to 930MHz Receiver
Evaluation Board Description
1
1.1
Theory of Operation
General
The MLX71121 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required
modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or
the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise filter (NF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize
power dissipation.
A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a
microcontroller. The clock output is open collector and gets activated through a load connected to positive
supply.
1.2
Technical Data Overview
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Input frequency ranges: 300 to 470MHz
610 to 930MHz
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Power supply range: 2.1 to 5.5V
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Temperature range: -40 to +125°C
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Shutdown current: 50 nA
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Operating current: 10.0 to 11.1mA
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Internal IF: 1.8MHz with 300kHz 3dB bandwidth
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FM/FSK deviation range: ±10kHz to ±100kHz
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Input Sensitivity: at 4kbps NRZ, BER = 3·10
-3
Frequency
FSK
ASK
Note:
internal IF2=1.8MHz, 300kHz BW,
Δf
= ±20kHz
internal IF2=1.8MHz, 300kHz BW
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315 MHz
-107dBm
-112dBm
433 MHz
-107dBm
-112dBm
868 MHz
-104dBm
-108dBm
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Image rejection:
65dB 1
st
IF (with external RF front-end filter)
25dB 2
nd
IF (internal image rejection)
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Maximum data rate: 50kps RZ (bi-phase) code,
100kps NRZ
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Spurious emission: < -54dBm
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Linear RSSI range: > 60dB
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Crystal reference frequency: 16 to 27MHz
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MCU clock frequency: 2.0 to 3.4MHz
915 MHz
-102dBm
-105dBm
- Sensitivities given for RF input 1 (without SAW filter)
- Sensitivity for RF input 2 is about 2 to 3dB worse (because of SAW filter loss)
39012 71121 01
Rev. 003
Page 3 of 18
EVB Description
Jan/08
EVB71121
300 to 930MHz Receiver
Evaluation Board Description
1.3
Block Diagram
VCC
IFSEL
MODSEL
LNAO2
MIXO
MIXN
VEE
2
LNAO1
MIXP
VEE
9
10
11
12
14
17
100k
16
100k
DF2
13
RSSI
DF1
3
6
4
5
27
24
ASK
OA1
SW1
100k
100k
DFO
18
LNAI1
1
LNA1
MIX1
MIX2
IFF
IFA
FSK
LNASEL
32
PKDET+
20
LNAI2
8
LO1
LO2
LNA2
N1
counter
VCO
BIAS
ENRX
FSK
DEMOD
PFD
RO
SW2
PDP
VEE
7
100k
PKDET_
PDN
21
RFSEL
31
SEQ
N2
counter
TEST
26
LF
CP
ROI
DIV 8
SLCSEL
CLKO
VCC
SLC
OA2
NCF
DTAO
29
CINT
22
19
23
30
25
28
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Fig. 1:
MLX71121 block diagram
The MLX71121 receiver IC consists of the following building blocks:
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PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.
The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback
divider chain (N1, N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a
crystal-based reference oscillator (RO).
Two low-noise amplifiers (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF Filter (IFF) with a 1.8MHz center frequency and a 300kHz 3dB bandwidth
IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detection mode.
Noise cancellation filter (NCF)
Sequencer circuit (SEQ) and biasing (BIAS) circuit
Clock output (DIV8)
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39012 71121 01
Rev. 003
Page 4 of 18
EVB Description
Jan/08
EVB71121
300 to 930MHz Receiver
Evaluation Board Description
1.4
Operating Modes
ENRX
0
1
Note:
ENRX is pulled down internally.
Description
Shutdown mode
Receive mode
1.5
Frequency Range
Two different receive frequency ranges can be selected by the control signal RFSEL.
RFSEL
0
1
Description
Input frequency range 300 to 470MHz
Input frequency range 610 to 930MHz
1.6
LNA Selection
LNASEL
0
Hi-Z
1
LNA1 shutdown, LNA2 active
Note: Hi-Z state means pin LNASEL is left floating (pin is internally pulled to V
CC
/2 in this case).
1.7
Demodulation Selection
MODSEL
0
1
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Description
LNA1 active, LNA2 shutdown
LNA1 and LNA2 active
Description
ASK demodulation
FSK demodulation
Description
Averaging detection mode
Peak detection mode
1.8
Data Slicer
SLCSEL
0
1
39012 71121 01
Rev. 003
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EVB Description
Jan/08
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