merging Memory & Logic Solutions Inc.
Document Title
128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
EM621FU16 Series
Low Power, 128Kx16 SRAM
Revision History
Revision No.
0.0
0.1
History
Initial Draft
2’nd Draft
Add Pb-free part number
Draft Date
December 18 , 2002
February 13 , 2004
Remark
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
merging Memory & Logic Solutions Inc.
FEATURES
•
•
•
•
•
•
Process Technology : 0.18µm Full CMOS
Organization : 128K x 16 bit
Power Supply Voltage : 2.7V ~ 3.3V
Low Data Retention Voltage : 1.5V(Min.)
Three state output and TTL Compatible
Package Type : 48-FPBGA 6.0x7.0
EM621FU16 Series
Low Power, 128Kx16 SRAM
GENERAL DESCRIPTION
The EM621FU16 families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
EM621FU16
Operating
Temperature
Industrial (-40 ~ 85
o
C)
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
1
µA
Operating
(I
CC1
.Max.)
2 mA
PKG Type
2.7V~3.3V
55
1)
/70ns
48 FPBGA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
1
A
B
C
D
E
F
G
H
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
LB
I/O
9
OE
UB
A
0
A
3
A
5
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
A
2
CS
I/O
2
I/O
4
I/O
5
I/O
6
WE
A
11
DNU
I/O
1
I/O
3
V
CC
V
SS
I/O
7
I/O
8
DNU
A A
11
A A A
14
A A
10
12
13
15
16
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Data
Cont
Data
Cont
V
C
C
Row S elect
V
SS
Memory Array
1024 x 2048
I/O
1 0
I/O
11
V
SS
V
C C
I/O
12
DNU
I/O
13
DNU
A
14
A
12
A
9
I/O1 ~ I/O8
I/O9 ~ I/O16
I/O Circuit
Column Select
I/O
1 5
I/O
14
I/O
1 6
DNU
DNU
A
8
48-FPBGA : Top view (ball down)
W
E
O
E
UB
Control Logic
Name
CS
OE
WE
A
0
~A
16
Function
Chip select input
Output Enable input
Write Enable input
Address Inputs
Name
Vcc
Vss
UB
LB
DNU
Function
Power Supply
Ground
Upper Byte (I/O
9~16
)
Lower Byte (I/O
1~8
)
Do Not Use
LB
CS
I/O
1
~I/O
16
Data Inputs/outputs
2
merging Memory & Logic Solutions Inc.
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Operating Temperature
EM621FU16 Series
Low Power, 128Kx16 SRAM
Symbol
V
IN
, V
OUT
V
CC
P
D
T
A
Ratings
-0.2 to Vcc+0.3 (Max. 4.0V)
-0.2 to 4.0V
1.0
-40 to 85
Unit
V
V
W
o
C
*
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
H
X
L
L
L
L
L
L
L
L
OE
X
X
H
H
L
L
L
X
X
X
WE
X
X
H
H
H
H
H
L
L
L
LB
X
H
L
X
L
H
L
L
H
L
UB
X
H
X
L
H
L
L
H
L
L
I/O
1-8
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
I/O
9-16
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Stand by
Stand by
Active
Active
Active
Active
Active
Active
Active
Active
Note: X means don’t care. (Must be low or high state)
3
merging Memory & Logic Solutions Inc.
RECOMMENDED DC OPERATING CONDITIONS
1)
Parameter
Supply voltage
Ground
Input high voltage
Input low voltage
1.
2.
3.
4.
EM621FU16 Series
Low Power, 128Kx16 SRAM
Symbol
V
CC
V
SS
V
IH
V
IL
Min
2.7
0
2.0
-0.2
3)
Typ
3.0
0
-
-
Max
3.3
0
V
CC
+ 0.2
2)
0.6
Unit
V
V
V
V
TA= -40 to 85
o
C, otherwise specified
Overshoot: V
CC
+2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested
.
CAPACITANCE
1)
(f =1MHz, T
A
=25
o
C)
Item
Input capacitance
Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current (TTL)
V
OL
V
OH
I
SB
V
IN
=V
S S
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
, LB=UB=V
IH
,
V
IO
=V
SS
to V
CC
I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS<0.2V, LB<0.2V or/and UB<0.2V,
V
IN
<0.2V or V
IN
>V
CC
-0.2V
Cycle time = Min, I
IO
=0mA, 100% duty,
CS=V
IL,
LB=V
IL
or/and UB=V
IL
, V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS=V
IH
, LB=UB =V
IH
Other inputs=V
IH
or V
IL
CS>V
CC
-0.2V(CS controlled) or
LB=UB
≥
V
CC
-0.2V, CS<0.2V(LB/UB Controlled)
Other inputs=0~V
CC
(Typ. condition : V
CC
=3.0V @
25
o
C)
(Max. condition : V
CC
=3.3V @ 85
o
C)
55ns
70ns
Test Conditions
Min
-1
-1
-
-
-
-
-
2.2
-
Typ Max
-
-
-
-
-
-
-
-
-
1
1
2
2
23
18
0.4
-
0.3
Unit
µA
µA
mA
mA
mA
V
V
mA
Standby Current (CMOS)
I
SB1
LL
LF
-
1
5
µA
4
merging Memory & Logic Solutions Inc.
AC OPERATING CONDITIONS
Test Conditions (Test
Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
= 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
CL
1)
EM621FU16 Series
Low Power, 128Kx16 SRAM
V
TM 3)
R
12)
CL
1)
R
22)
READ CYCLE
(V
cc
=2.7 to 3.3V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB acess time
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Symbol
t
RC
t
AA
t
co
t
O E
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
55ns
Min
55
-
-
-
Max
-
55
55
30
55
10
10
5
0
0
0
15
-
-
-
20
20
20
-
10
10
5
0
0
0
15
Min
70
-
-
-
70ns
Max
-
70
70
35
70
-
-
-
25
25
25
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(V
cc
=2.7 to 3.3V, Gnd = 0V, T
A
= -40
o
C to +85
o
C)
Parameter
Write cycle time
Chip select to end of write
Address setup time
Address valid to end of write
UB, LB valid to end of write
Write pulse width
Write recovery time
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
t
WC
t
CW
t
As
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55ns
Min
55
45
0
45
45
40
0
0
25
0
5
-
-
Max
-
-
-
-
-
-
-
20
Min
70
60
0
60
60
55
0
0
30
0
5
70ns
Max
-
-
-
-
-
-
-
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
ns
ns
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