ABRIDGED DATA SHEET
219-0008; Rev 1; 3/12
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
General Description
The DS28E02 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the FIPS 180-3 Secure Hash Algorithm
(SHA-1). The 1024-bit EEPROM array is configured as
four pages of 256 bits with a 64-bit scratchpad to per-
form write operations. All memory pages can be write
protected, and one page can be put in EPROM-emula-
tion mode, where bits can only be changed from a 1 to
a 0 state. Each DS28E02 has its own guaranteed
unique 64-bit ROM registration number that is factory
installed into the chip. The DS28E02 communicates
over the single-contact 1-Wire
®
bus. The communica-
tion follows the standard 1-Wire protocol with the regis-
tration number acting as the node address in the case
of a multidevice 1-Wire network.
Features
o
1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
o
On-Chip 512-Bit SHA-1 Engine to Compute 160-
Bit Message Authentication Codes (MACs) and to
Generate Secrets
o
Write Access Requires Knowledge of the Secret
and the Capability of Computing and Transmitting
a 160-Bit MAC as Authorization
o
User-Programmable Page Write Protection for
Page 0, Page 3, or All Four Pages Together
o
User-Programmable OTP EPROM Emulation Mode
for Page 1 (“Write to 0”)
o
Communicates to Host with a Single Digital
Signal at 12.5kbps or 35.7kbps Using 1-Wire
Protocol
o
Switchpoint Hysteresis and Filtering to Optimize
Communication Performance in the Presence of
Noise
o
Reads and Writes Over 1.75V to 3.65V Voltage
Range from -20°C to +85°C
o
6-Lead TSOC and TDFN Packages
DS28E02
Applications
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Medical Consumable Authentication
Printer Cartridge Configuration and Monitoring
Typical Operating Circuit
PART
V
CC
R
PUP
IO
µC
DS28E02
Ordering Information
TEMP RANGE
-20°C to +85°C
-20°C to +85°C
-20°C to +85°C
PIN-PACKAGE
6 TSOC
6 TSOC
6 TDFN-EP*
(2.5k pcs)
DS28E02P+
DS28E02P+T&R
DS28E02Q+T&R
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP
= Exposed pad.
GND
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
ABRIDGED DATA SHEET
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
DS28E02
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .......................................-0.5V to +4V
IO Sink Current ...................................................................20mA
Operating Temperature Range ...........................-20°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -20°C to +85°C.) (Note 1)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
SYMBOL
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
(Note 2)
(Notes 2, 3)
(Notes 4, 5)
IO pin at V
PUP
(Notes 5, 6, 7)
(Notes 2, 8)
(Notes 5, 6, 9)
0.74
0.26
20
20
80
28
480
50
480
48
60
7
60
8
1
1
5
1
t
RL
+
t
RL
+
640
80
CONDITIONS
MIN
1.75
300
1500
0.05
0.4
5
V
PUP
–
0.89
0.30
V
PUP
–
0.49
1.02
0.4
TYP
MAX
3.65
750
UNITS
V
pF
µA
V
V
V
V
V
µs
µs
(Notes 5, 6, 10)
At 4mA current load (Note 11)
Standard speed, RPUP = 750
Recovery Time (Notes 2, 12)
t
REC
Overdrive speed
Standard speed
Time Slot Duration (Notes 2, 13)
t
SLOT
Overdrive speed
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed
Reset Low Time (Note 2)
t
RSTL
Overdrive speed
Standard speed
Reset High Time (Note 14)
t
RSTH
Overdrive speed
Standard speed
Presence-Detect Sample Time
t
MSP
(Notes 2, 15)
Overdrive speed
IO PIN: 1-Wire WRITE
Standard speed
Write-Zero Low Time (Notes 2, 16)
t
W0L
Overdrive speed
Standard speed
Write-One Low Time (Notes 2, 16)
t
W1L
Overdrive speed
IO PIN: 1-Wire READ
Standard speed
Read Low Time (Notes 2, 17)
t
RL
Overdrive speed
Standard speed
Read Sample Time (Notes 2, 17)
t
MSR
Overdrive speed
EEPROM
IO voltage < 3.65V
Programming Current
I
PROG
IO voltage < 2.95V
(Notes 5, 18)
IO voltage = 1.75V
µs
µs
72
10
120
15.5
15
2
15 -
2-
15
2
3.5
2.5
1.0
µs
µs
µs
µs
µs
mA
2
_______________________________________________________________________________________
ABRIDGED DATA SHEET
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -20°C to +85°C.) (Note 1)
PARAMETER
Programming Time
Write/Erase Cycles (Endurance)
(Notes 20, 21)
Data Retention (Notes 22, 23, 24)
SHA-1 ENGINE
Computation Current
Computation Time (Notes 5, 25)
SYMBOL
t
PROG
N
CY
t
DR
I
LCSHA
t
CSHA
(Note 19)
At +25°C
At +85°C
At +85°C
(Notes 5, 18)
CONDITIONS
MIN
200,000
50,000
40
TYP
MAX
25
UNITS
ms
—
Years
mA
ms
DS28E02
Refer to full data sheet
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Maximum value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic 0 level.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
An additional reset or communication sequence cannot begin until the reset high time has expired.
Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E02 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
ε
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
-
ε
and t
W0LMAX
+ t
F
-
ε,
respectively.
δ
in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Current drawn from IO during the EEPROM programming interval or SHA-1 computation.
Note 19: Refer to full data sheet for this note.
Note 20:
Note 21:
Note 22:
Note 23:
Write-cycle endurance is degraded as T
A
increases.
Not 100% production tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 24:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Note 25: Refer to full data sheet for this note.
_______________________________________________________________________________________
3
ABRIDGED DATA SHEET
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
DS28E02
Pin Configurations
TOP VIEW
TOP VIEW
+
GND
IO
N.C.
1
2
3
6 N.C.
N.C.
1
2802
ymrrF
DS28E02
+
6
N.C.
DS28E02
5
4
N.C.
N.C.
IO
2
5
N.C.
TSOC
GND
3
EP
4
N.C.
TDFN
(3mm
×
3mm)
Pin Description
PIN
TSOC
1
2
3, 4, 5, 6
—
TDFN-EP
3
2
1, 4, 5, 6
—
NAME
GND
IO
N.C.
EP
Ground Reference
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Not Connected
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper
operation. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction
for
additional information.
FUNCTION
Detailed Description
The DS28E02 combines 1024 bits of EEPROM orga-
nized as four 256-bit pages, a 64-bit secret, a register
page, a 512-bit SHA-1 engine, and a 64-bit ROM regis-
tration number in a single chip. Data is transferred seri-
ally through the 1-Wire protocol, which requires only a
single data lead and a ground return. The DS28E02
has an additional memory area called the scratchpad
that acts as a buffer when writing to the memory, the
register page, or when installing a new secret. Data is
first written to the scratchpad from where it can be read
back. After the data has been verified, a copy scratch-
pad command transfers the data to its final memory
location, provided that the DS28E02 receives a match-
ing 160-bit MAC. The computation of the MAC involves
the secret and additional data stored in the DS28E02
including the device’s registration number. The
DS28E02 understands a unique command “Refresh
Scratchpad.” Proper use of a refresh sequence after a
copy scratchpad operation reduces the number of
weak bit failures if the device is used in a touch envi-
ronment (see the
Writing with Verification
section). The
refresh sequence also provides a means to restore
functionality in a device with bits in a weak state.
In addition to its important use as a unique data value in
cryptographic SHA-1 computations, the device's 64-bit
ROM ID guarantees unique identification and can be
used to electronically identify the equipment in which it is
used. The ROM ID is also used to address the device for
the case of a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus
and operate independently of each other. Applications of
the DS28E02 include reference design license manage-
ment, system intellectual property protection, accessory
4
_______________________________________________________________________________________
ABRIDGED DATA SHEET
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
DS28E02
PARASITE POWER
1-Wire NET
1-Wire FUNCTION
CONTROL
64-BIT
ROM
MEMORY AND
SHA-1 FUNCTION
CONTROL UNIT
512-BIT
SECURE HASH
ALGORITHM ENGINE
DS28E02
CRC16
GENERATOR
64-BIT
SCRATCHPAD
DATA MEMORY
4 PAGES OF
256 BITS EACH
REGISTER
PAGE
Figure 1. Block Diagram
or consumable authentication and calibration, and
printer cartridge configuration and monitoring.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E02. The DS28E02 has six main data compo-
nents: 64-bit ROM, 64-bit scratchpad, four 256-bit
pages of EEPROM, register page, and a 512-bit SHA-1
engine. Figure 2 shows the hierarchic structure of the
1-Wire protocol. The bus master must first provide one
of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, Resume
Communication, Overdrive-Skip ROM, or Overdrive-
Match ROM. Upon completion of an Overdrive-Skip
ROM or Overdrive-Match ROM command executed at
standard speed, the device enters overdrive mode
where all subsequent communication occurs at a higher
speed. The protocol required for these ROM function
commands is described in Figure 10. After a ROM
function command is successfully executed, the mem-
ory and SHA-1 functions become accessible and the
master can provide any one of the 9 available function
commands. The function protocols are described in
Figure 8.
All data is read and written least signifi-
cant bit first.
64-Bit ROM
Each DS28E02 contains a unique ROM registration num-
ber that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a cyclic redundancy check (CRC) of the
first 56 bits. See Figure 3 for details. The 1-Wire CRC is
generated using a polynomial generator consisting of a
shift register and XOR gates as shown in Figure 4. The
polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information
about the 1-Wire CRC is available in Application Note
5
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