DS1747/DS1747P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FEATURES
Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control
Circuit, and Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations
Century Byte Register (Y2K Compliant)
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the Year 2100
Battery Voltage-Level Indicator Flag
Power-Fail Write Protection Allows for
±10% V
CC
Power-Supply Tolerance
PIN CONFIGURATIONS
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
Maxim
2
DS1747
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only:
Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
PowerCap Module Board Only:
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
Also Available in Industrial Temperature
Range: -40°C to +85°C
Encapsulated DIP
(512k x 8)
N.C.
A15
A16
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1747P
Maxim
X1
GND
V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
PowerCap Module Board
1 of 16
19-5504; Rev 6/13
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
EDIP
1
2
3
4
5
6
7
8
9
10
11
12
23
25
26
27
28
30
31
13
14
15
17
18
19
20
21
16
22
24
29
32
—
—
—
—
PIN
PowerCap
34
3
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
33
2
16
15
14
13
12
11
10
9
17
8
7
6
5
1
4
NAME
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
A8
A13
A17
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
OE
WE
V
CC
N.C.
RST
X1, X2
V
BAT
FUNCTION
Address Input
Data Input/Output
(See
Pin
Configuration)
(See
Pin
Configuration)
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
Power-Supply Input
No Connection
Active-Low Power-On Reset Output
Crystal Input, Output Connections
Battery Connection
2 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART
DS1747-70+
DS1747-70IND+
DS1747P-70+
DS1747P-70IND+
DS1747W-120+
DS1747W-120IND+
DS1747WP-120+
DS1747WP-120IND+
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX+
or DS9034I-PCX+ required (must be ordered separately).
†
A “+” indicates lead(Pb)-free. The top mark will include a “+” symbol on lead(Pb)-free devices.
SUPPLY
VOLTAGE
(V)
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
TOP MARK
†
DS1747-70+
DS1747-70IND+
DS1747P+70
DS1747P+70 IND
DS1747W-120+
DS1747W-120IND+
DS1747WP+120
DS1747WP+120 IND
DESCRIPTION
The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1747 also
contains its own power-fail circuitry that deselects the device when the V
CC
supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on
by low V
CC
as errant access and update cycles are avoided.
3 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Maxim
DS1747
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers.
PACKAGES
TIME AND DATE OPERATIONS
The contents of the time and date registers are in BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register (see
Table 2). As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500µs to ensure the external registers will be updated.
4 of 16
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
V
CC
V
CC
>V
PF
V
SO
<V
CC
<V
PF
V
CC
<V
SO
<V
PF
CE
V
IH
V
IL
V
IL
V
IL
X
X
OE
X
X
V
IL
V
IH
X
X
WE
X
V
IL
V
IH
V
IH
X
X
MODE
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Active
Active
Active
CMOS Standby
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the device registers. The user can subsequently load correct date and time values into all eight registers,
followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings
into the clock, allowing timekeeping operations to resume from the new set point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the device registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the
previous set point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write
cycle to Control if the W bit is being cleared to 0 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write
cycle to Control if the R bit is being cleared to 0 in that write operation.
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
STOPPING AND STARTING THE CLOCK OSCILLATOR
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within
±1
minute per month at +25°C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The
5 of 16
京公网安备 11010802033920号
EEWORLD
