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TC55VZM208AFTN10

Description
IC 512K X 8 CACHE SRAM, 10 ns, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44, Static RAM
Categorystorage    storage   
File Size158KB,10 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Download Datasheet Parametric View All

TC55VZM208AFTN10 Overview

IC 512K X 8 CACHE SRAM, 10 ns, PDSO44, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44, Static RAM

TC55VZM208AFTN10 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerToshiba Semiconductor
Parts packaging codeTSOP2
package instructionTSOP2, TSOP44,.46,32
Contacts44
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time10 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G44
JESD-609 codee0
length18.41 mm
memory density4194304 bi
Memory IC TypeCACHE SRAM
memory width8
Number of functions1
Number of terminals44
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.004 A
Minimum standby current3 V
Maximum slew rate0.15 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.16 mm
TC55VZM208AJJN/AFTN08,10,12
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55VZM208AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as
524,288 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed,
it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55VZM208AJJN/AFTN is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width
for high density surface assembly.
FEATURES
Fast access time (the following are maximum values)
TC55VZM208AJJN/AFTN08:8 ns
TC55VZM208AJJN/AFTN10:10 ns
TC55VZM208AJJN/AFTN12:12 ns
Low-power dissipation (I
DDO2
)
(the following are maximum values)
Cycle Time
Operation (max)
8
130
10
120
12
110
ns
mA
Single power supply voltage of 3.3 V
±
0.3 V
Fully static operation
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Package:
SOJ36-P-400-1.27 (AJJN)
(Weight: 1.35 g typ)
TSOP II44-P-400-0.80 (AFTN) (Weight: 0.45 g typ)
Standby:4 mA (both devices)
PIN ASSIGNMENT
(TOP VIEW)
36 PIN SOJ
44 PIN TSOP
PIN NAMES
A0 to A18
NC
NC
A17
A3
A2
A1
A0
CE
I/O1
I/O2
V
DD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
DD
I/O6
I/O5
A8
A9
A10
A11
A12
NU
NC
NC
I/O1 to I/O8
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+3.3 V)
Ground
No Connection
Not Usable (Input)
A17
A3
A2
A1
A0
CE
I/O1
I/O2
V
DD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
DD
I/O6
I/O5
A8
A9
A10
A11
A12
NU
WE
OE
V
DD
GND
NC
NU
(TC55VZM208AJJN)
(TC55VZM208AFTN)
2003-01-17
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