SUMMIT
MICROELECTRONICS, Inc.
SMP9317
Nonvolatile DACPOT™ Electronic Potentiometer
With Up/Down Counter Interface
FEATURES
• Digitally Controlled Electronic Potentiometer
• 7-Bit Digital-to-Analog Converter (DAC)
– Independent Reference Inputs
– Differential Non-Linearity - +0.5LSB
– Integral Non-Linearity - +1LSB
• V
OUT
Value in EEPROM for Power-On Recall
– Equivalent to 128-Step Potentiometer
• Unity Gain Op Amp Drives
±
100
µ
A
• Simple Trimming Adjustment
– Up/Down Counter Style Operation
• Low Noise Operation
• “Clickless” Transitions between DAC Steps
• No Mechanical Wearout Problem
– 1,000,000 Stores (typical)
– 100 Year Data Retention
• Operation from +2.7V to +5.5V Supply
• Ultra-Low Power, 0.5mW max at +5V
OVERVIEW
The SMP9317 DACPOT™ trimmer is a 7-bit nonvolatile
DAC designed to replace mechanical potentiometers.
The SMP9317 includes a unity-gain amplifier to buffer the
DAC output and enables V
OUT
to swing from rail to rail.
The DACPOT trimmer operates over a supply voltage
range of 2.7V to 5.5V.
The SMP9317’s simple up/down counter input provides
an ideal interface for automatic test equipment to dither
and monitor the V
OUT
voltage. This interface allows for
quick and consistent calibration of even the most sophis-
ticated systems.
The SMP9317 is a pin-compatible performance upgrade
for other industry nonvolatile potentiometers. The
SMP9317 offers higher resolution than these devices and
provides ‘clickless’ transitions of V
OUT
.
FUNCTIONAL BLOCK DIAGRAM
VDD
7-bit E2 PROM
VH
-
UP/DN
INC
CS
Counter
&
Write
Control
7-bit
Data
Register
AMP
7-bit DAC
+
VOUT
VL
GND
2031 ILL2.0
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 1998
2031-04 12/4/98
1
Characteristics subject to change without notice
SMP9317
PIN NAMES
Symbol
INC
UP/DN
V
H
GND
V
OUT
V
L
CS
V
DD
Description
Increment Input, High to Low
Edge Trigger
Up/Down Input controlling relative
V
OUT
movement
V+ reference input
Analog and Digital Ground
Trimmed Voltage Output
V- reference input
Active low chip select input
Supply Voltage (2.7V to 5.5V)
Increment (INC
is an edge triggered input. Whenever
INC)
INC
CS
is low and a high to low transition occurs on the
INC
input, the V
OUT
voltage will either move toward V
H
or V
L
depending upon the state of the UP/DN input.
DN
UP/Down (UP/DN
is an input that will determine the V
OUT
DN)
movement relative to V
H
and V
L
. When
CS
is low, UP/DN
is high and there is a high to low transition on
INC,
the
V
OUT
voltage will move (1/128
th
x V
H
-V
L
) toward V
H
.
When
CS
and UP/DN are low, and there is a high to low
transition on
INC,
the V
OUT
will move (1/128
th
x V
H
-V
L
)
toward V
L
.
Power–Up/Power–Down Conditions
On power–up the SMP9317 loads the value of EEPROM
memory into the wiper position register. The value in the
register is changed using the
CS, INC,
and UP/DN pins.
The new data in the register will be lost at power-down
unless
CS
was brought high, with
INC
high, to initiate a
store operation after the last increment or decrement. On
the next device power–up, the value of EEPROM memory
will be loaded into the wiper position register. During
power-up the SMP9317 is write-protected in two ways:
1) A power-on reset, that trips at approximately 2.5V,
holds
CS
and
INC
high internally.
2) Resistor pull-ups on all logic inputs prevent data
change if the inputs are floating.
Data Retention
The SMP9317 is guaranteed to perform at least
1,000,000 writes to EEPROM before a wear–out condi-
tion can occur. After EEPROM wearout, the SMP9317
continues to function as a volatile digital-potentiometer.
The wiper position can be changed during powered
conditions using the digital interface. However, on power–
up the wiper–position will be indeterminate.
On shipment from the factory, Summit Microelectronics
does not specify any EEPROM memory value. The value
must be set by the customer as needed.
2031 ILL1.0
PINOUT
INC
UP/DN
VH
GND
1
2
3
4
8
7
6
5
VDD
CS
VL
VOUT
Analog Section
The SMP9317 is a 7-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts a 7-bit value into equivalent analog output
voltages in proportion to the applied reference voltage.
Reference Inputs
The voltage differential between the V
L
and V
H
inputs
sets the full-scale output voltage range. V
L
must be equal
to or greater than ground (i.e. a positive voltage). V
H
must
be greater than V
L
and less than or equal to V
DD
. See
table on page 3 for guaranteed operating limits.
Output Buffer Amplifier
The voltage output is from a precision unity-gain follower
that can slew up to 1V/µs.
Digital Interface
The interface is designed to emulate a simple up/down
counter, but instead of a parallel count output, a
ratiometric voltage output is provided.
Chip Select (CS
is an active low input. Whenever
CS
is
CS)
CS
high the SMP9317 is in standby mode and consumes the
least power. This mode is equivalent to a potentiometer
that is adjusted to the required setting. When
CS
is low
the SMP9317 will recognize transitions on the
INC
input
and will move the V
OUT
either toward the V
H
reference or
toward the V
L
reference depending upon the state of the
UP/DN input.
The host may exit an adjustment routine in two ways:
deselecting the SMP9317 while
INC
is low will not per-
form a store operation (a subsequent power cycle will
recall the original data); deselecting the SMP9317 while
INC
is high will store the current V
OUT
setting into non-
volatile memory.
2031-04 12/4/98
2
SMP9317
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Storage Temperature
Voltage on pins with reference to GND:
Analog Inputs
Digital Inputs
Analog Outputs
Digital Outputs
Lead Solder Temperature (10 secs)
-55°C to +125°C
-65°C to +150°C
-0.5V to V
DD
+.5V
-0.5V to V
DD
+.5V
-0.5V to V
DD
+.5V
-0.5V to V
DD
+.5V
300°C
*COMMENT
Stresses above those listed under Absolute Maxi-
mum Ratings may cause permanent damage to
the device. These are stress ratings only, and
functional operation of the device at these or any
other conditions outside those listed in the opera-
tion sections of this specification is not implied.
Exposure to any absolute maximum rating for
extended periods may affect device performance
and reliability.
RECOMMENDED OPERATING CONDITIONS
Condition
Temperature
V
DD
Min
-40°C
+2.7V
Max
+85°C
+5.5V
2031 PGM T1.0
DAC DC ELECTRICAL CHARACTERISTICS
V
DD
= +2.7V to +5.5V, V
refH
= V
DD
, V
refL
= 0V, T
A
= -40°C to +85°C, unless specified otherwise
Symbol
Parameter
Integral Non-Linearity
Conditions
I
LOAD
= 50µA,
I
LOAD
= 100µA,
DNL
Differential Non-Linearity
I
LOAD
= 50µA,
I
LOAD
= 100µA,
T
R
= C
T
R
= I
T
R
=C
T
R
= I
T
R
= C
T
R
= I
T
R
= C
T
R
= I
Min.
-
-
-
-
-
-
-
-
2.5
V
H
≥
V
L
Gnd
-
V
refH
to V
refL
DATA = 7F
-
-
0
-
-
Typ.
0.6
0.6
1.2
1.2
0.25
0.25
0.5
0.5
-
-
38K
700
-
Max.
±1
±1
-
-
±0.5
±0.5
-
-
V
DD
V
DD
-2.5
-
-
±1
20
200
100
+5V
+3V
-
-
-
-
-
-
10
20
-
90
0.08
1,000
1
-
-
-
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
V
V
Ω
ppm/°C
LSB
mV
µV/°C
µA
Ω
Ω
LSB/V
nV/
%
kHz
2031 PGM T3.2
2031-04 12/4/98
Accuracy
INL
References
V
H
V
L
R
IN
TCR
IN
V
refH
Input Voltage
V
refL
Input Voltage
V
refH
to V
refL
Resistance
Temperature Coefficient
of R
IN
Full-Scale Gain Error
Analog
Output
G
EFS
V
OUT
ZS
TCV
OUT
I
L
R
OUT
PSRR
e
N
THD
BW
Zero-Scale Output Voltage DATA = 00
V
OUT
Temperature
Coefficient, note 3
Amplifier Output Load Current
Amplifier Output Resistance I
L
= 100µA
Power Supply Rejection
Amplifier Output Noise
Total Harmonic Distortion
Bandwidth - 3dB
I
LOAD
= 10µA
f = 1KHz, V
DD
= +5V
V
IN
= 1V rms, f = 1KHz
V
IN
= 100mV rms
3
V
DD
= +5, I
LOAD
= 50µA,
V
refH
= +5V, V
refL
= 0V
H
Z
SMP9317
RELIABILITY CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol
VZAP
ILTH
TDR
NEND
Parameter
ESD Susceptibility
Latch-Up
Data Retention
Endurance
Min
2000
100
100
1,000,000
Max
Unit
V
mA
Years
Stores
Test Method
MS-883, TM 3015
JEDEC Standard 17
MS-883, TM 1008
MS-883, TM 1033
2031 PGM T2.0
DC ELECTRICAL CHARACTERISTICS
V
DD
= +2.7V to +5.5V, V
H
= V
DD
, V
L
= 0V, T
A
= -40°C to +85°C, Unless otherwise specified
Symbol
I
DD
I
SB
I
IH
I
IL
V
IH
V
IL
Notes:
1. I
DD
is the supply current drawn while the EEPROM is being updated. I
DD
does not include the current that flows through the Reference
resistor chain.
2.
CS,
UP/DN and
INC
have internal pull-up resistors of approximately 200kΩ. When the input is pulled to ground the resulting output
current will be V
DD
/200kΩ.
3. TCV
OUT
is guaranteed but not tested.
Parameter
Supply Current
during store, note 1
Supply Standby Current
Input Leakage Current
Input Leakage Current, note 2
High Level Input Voltage
Low Level Input Voltage
Conditions
CS = V
IL
to V
IH
W/INC HI
CS = V
IH
V
IN
= V
DD
V
IN
= 0V
Min
Typ
1.0
Max
Units
mA
100
10
-25
2
V
DD
0.8
µA
µA
µA
V
V
2031 PGM T4.1
V
DD
≥
4.5V
0
2031-04 12/4/98
4
SMP9317
OPERATIONAL TRUTH TABLE
INC
HI
TO
LO
HI
TO
LO
H
L
X
CS
L
L
LO
TO
HI
LO
TO
HI
H
UP/DN
DN
H
L
X
X
X
Operation
V
OUT
toward V
H
V
OUT
toward V
L
Store Setting
Maintain Setting, NO Store
Standby, note 1
2031 PGM T5.1
Notes:
1. The Standby or operating current will be lowest with
INC
and UP/DN pins at H as there are weak internal pull-ups that draw current
when connected LO.
AC TIMING CHARACTERISTICS
Symbol
t
CLIL
t
IHDC
t
DCIL
t
IL
t
IH
t
IHCH
t
WP
t
ILVOUT
Parameter
CS
to
INC
Setup
INC
High to UP/DN Change
UP/DN to
INC
Setup
INC
Low Period
INC
High Period
INC
Inactive to
CS
Inactive
Write
Cycle Time
INC
to V
OUT
Delay
Min
100
100
100
200
200
100
5
5
Max
Units
ns
ns
ns
ns
ns
ns
ms
µs
2031 PGM T6.0
CS
t
CLIL
t
IL
t
IH
t
IHCH
t
WP
INC
t
IHDC
UP/DN
t
DCIL
t
ILVOUT
VOUT
2031 ILL3.1
AC TIMING DIAGRAM
2031-04 12/4/98
5
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