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The PC107 PCI Bridge/Integrated Memory Controller provides a bridge between the Peripheral Component
Interconnect (PCI) bus and PC6xx, PC7xx, and PC74xx microprocessors. PCI support allows system designers
to design systems quickly using peripherals already designed for PCI and the other standard interfaces available
in the personal computer hardware environment. The PC107 provides many of the other necessities for
embedded applications, including a high-performance memory controller and dual-processor support; two-
channel flexible DMA controller; an interrupt controller; an I
2
O-ready message unit; an inter-integrated circuit
controller (I
2
C); and low-skew clock drivers. The PC107 contains an Embedded Programmable Interrupt
Controller (EPIC) featuring five hardware interrupts (IRQs) as well as 16 serial interrupts along with four timers.
The PC107 uses an advanced, 2.5V HiP3 process technology and is fully compatible with TTL devices.
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- Four levels of power reduction–doze, nap, sleep, and suspend
- Fully static, internal logic states preserved during all power modes
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The memory interface controls processor and PCI interactions to main memory.
It supports a variety of programmable timing supporting DRAM (FPM, EDO), SDRAM,
and ROM/Flash ROM configurations, up to speeds of 100 MHz.
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The PC107 PCI interface is designed to connect the processor and memory buses to the
PCI local bus without the need for “glue” logic at speeds up to 66 MHz.
The PC107 acts as either a master or slave device on the PCI bus and contains a PCI
bus arbitration unit which reduces the need for an equivalent external unit, thus reducing
the total system complexity and cost.
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The PC107 supports a programmable interface to microprocessors implementing the
PowerPC architecture operating at bus frequencies up to 100 MHz. The PC107
processor interface allows for a variety of system configurations by providing support for
a second processor and a local bus slave.
60x Bus
Data Path
ECC/Pariy
Unit
Memory
Data
I
2
O
Processor
Interface Unit
DMA
Central
Control Unit
Memory
Controller
Memory
Add/Cntl
Mem Clocks
I
2
C
I
2
C
PCI
Interface Unit
IRQs
PLL
EPIC
ATU
Timers
Arbiter
FO
Buffer
PCI Clocks
DLL
Clock In
PCI Bus
REQ/GNT
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PC107 - Rev.5 – 01/04
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- High-bandwidth (32-bit/64-bit) data bus up to 100 MHz
- Programmable timing supporting either DRAM (FPM, EDO) or SDRAM
- Supports one to eight banks – 4-, 16-, 64-, 128-, and/or 256-bit DRAMs or SDRAMs
- 1 GB of RAM space, 144 MB of ROM space
- 8-, 32-, or 64-bit ROM/Flash ROM
- PortX: 8-, 32-, or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
- Supports parity, read-modify-write, or error-correcting code (ECC)
- Processor bus frequency up to 100 MHz
- 64-bit or 32-bit data bus and 32-bit address bus
- SMP support for a second processor
- Full memory coherency supported, integrated arbiter, and slave peripheral support
- Supports PC6xx, PC7xx, and PC74xx processors
- Compliant with PCI specification, revision 2.1
- 32-bit PCI interface operates up to 66 MHz
- 5.0V compatible
- Read and write buffers to improve PCI performance
- Selectable big- or little-endian operation
- PCI interface can be configured as host or agent, allowing multiple PC107 chips on same PCI bus
- Arbiter supports up to five other PCI devices
- Parity support
PCI to local memory, Local to PCI memory
- Message Unit: Intelligent Input/Output (I
2
O) Message Controller, 2 door-bell registers, Inbound and outbound messaging registers
- Inter-Integrated Circuit (I2C) Controlle: Full master/slave support
- Embedded programmable interrupt controller (EPIC): 5 hardware interrupts (IRQs) or 16 serial interrupts, 4 programmable timers
- Integrated PCI bus and SDRAM clock generation
- Programmable memory and PCI bus drivers
- Debug Features: Watchpoint monitor, Memory attribute and PCI attribute signals, JTAG/COP hardware debugging
IEEE 1149.1-compliant, JTAG boundary-scan interface
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Two-channel integrated DMA controller: Local to local memory, PCI to PCI memory,
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The PC107 PCI Bridge/Memory Controller is available in the following package:
- 503-ball Flip-Chip Plastic Ball Grid Array (FC-PBGA)
- 503-ball Flip-Chip Hi-TCE Ceramic Ball Grid Array (CBGA)
- FC-PBGA upscreening based upon ATMEL-Grenoble standards
- Full military temperature range: Tj = -55°C to +125°C
- Industrial temperature range:
Tj = -40°C to +110°C
Q8 &6
Type
(PCX107A if prototype)
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M: -55, +125°C
V: -40, +110°C
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GH: Hi-TCE
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100 MHz
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U: Upscreening
For availability of the different version, please contact your Atmel sales office
or visit our web site at http://www.atmel.com
You may also contact the PowerPC technical hotline at std.hotline@gfo.atmel.com
Specifications and information herein are subject to change without notice.
BP123 - 38521 Saint-Egrève Cedex - France - Tel: +33 (0)4 76 58 30 00 - Fax: +33 (0)4 76 58 34 80