PHD45N03LT datasheet, PDF - EEWORLD Datasheet

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PHD45N03LT: Description45A, 25V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, DPAK-3; CategoryDiscrete semiconductor The transistor; File Size45KB，6 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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PHD45N03LT Overview

45A, 25V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, DPAK-3

PHD45N03LT Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	SMALL OUTLINE, R-PSSO-G2
Contacts	3
Reach Compliance Code	unknow
ECCN code	EAR99
Avalanche Energy Efficiency Rating (Eas)	60 mJ
Shell connection	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	25 V
Maximum drain current (ID)	45 A
Maximum drain-source on-resistance	0.024 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-PSSO-G2
Number of components	1
Number of terminals	2
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	175 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Polarity/channel type	N-CHANNEL
Maximum power consumption environment	86 W
Maximum pulsed drain current (IDM)	180 A
Certification status	Not Qualified
surface mount	YES
Terminal form	GULL WING
Terminal location	SINGLE
transistor applications	SWITCHING
Transistor component materials	SILICON
Maximum off time (toff)	105 ns
Maximum opening time (tons)	150 ns

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Philips Semiconductors

Product specification

TrenchMOS™ transistor

Logic level FET

FEATURES

•

’Trench’

technology

• Very low on-state resistance

• Fast switching

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

PHP45N03LT, PHB45N03LT, PHD45N03LT

SYMBOL

QUICK REFERENCE DATA

DSS

= 30 V

= 45 A

DS(ON)

≤

24 mΩ (V

= 5 V)

DS(ON)

≤

21 mΩ (V

= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB45N03LT is supplied in the SOT404 surface mounting package.

The PHD45N03LT is supplied in the SOT428 surface mounting package.

PINNING

tab

DESCRIPTION

SOT78 (TO220AB)

tab

SOT404

tab

SOT428

tab

gate

drain

source

drain

1 23

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

DSS

DGR

, T

stg

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

CONDITIONS

= 25 ˚C to 175˚C

= 25 ˚C to 175˚C; R

= 20 kΩ

= 25 ˚C; V

= 10 V

= 100 ˚C; V

= 10 V

= 25 ˚C

MIN.

- 55

MAX.

180

175

UNIT

˚C

It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.

January 1998

Rev 1.300

PHD45N03LT Related Products

	PHD45N03LT	PHB45N03LT	PHB45N03LT/T3	PHB45N03LTT/R	PHP45N03LT
Description	45A, 25V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, DPAK-3	45A, 25V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3	TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power	TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power	TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, PLASTIC, TO-220AB, 3 PIN, FET General Purpose Power
Maker	NXP	NXP	NXP	NXP	NXP
package instruction	SMALL OUTLINE, R-PSSO-G2	SMALL OUTLINE, R-PSSO-G2	SMALL OUTLINE, R-PSSO-G2	SMALL OUTLINE, R-PSSO-G2	FLANGE MOUNT, R-PSFM-T3
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Avalanche Energy Efficiency Rating (Eas)	60 mJ	60 mJ	60 mJ	60 mJ	60 mJ
Shell connection	DRAIN	DRAIN	DRAIN	DRAIN	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	25 V	25 V	25 V	25 V	25 V
Maximum drain current (ID)	45 A	45 A	45 A	45 A	45 A
Maximum drain-source on-resistance	0.024 Ω	0.024 Ω	0.024 Ω	0.024 Ω	0.024 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-PSSO-G2	R-PSSO-G2	R-PSSO-G2	R-PSSO-G2	R-PSFM-T3
Number of components	1	1	1	1	1
Number of terminals	2	2	2	2	3
Operating mode	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE
Maximum operating temperature	175 °C	175 °C	175 °C	175 °C	175 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	FLANGE MOUNT
Polarity/channel type	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL
Maximum power consumption environment	86 W	86 W	86 W	86 W	86 W
Maximum pulsed drain current (IDM)	180 A	180 A	180 A	180 A	180 A
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES	YES	NO
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	THROUGH-HOLE
Terminal location	SINGLE	SINGLE	SINGLE	SINGLE	SINGLE
transistor applications	SWITCHING	SWITCHING	SWITCHING	SWITCHING	SWITCHING
Transistor component materials	SILICON	SILICON	SILICON	SILICON	SILICON
Maximum off time (toff)	105 ns	105 ns	105 ns	105 ns	105 ns
Maximum opening time (tons)	150 ns	150 ns	150 ns	150 ns	150 ns
Contacts	3	3	3	-	3

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