Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
PHP45N03LT, PHB45N03LT, PHD45N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 45 A
g
R
DS(ON)
≤
24 mΩ (V
GS
= 5 V)
R
DS(ON)
≤
21 mΩ (V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB45N03LT is supplied in the SOT404 surface mounting package.
The PHD45N03LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate
drain
1
source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C; V
GS
= 10 V
T
mb
= 100 ˚C; V
GS
= 10 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
15
45
33
180
86
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
January 1998
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
PHP45N03LT, PHB45N03LT, PHD45N03LT
CONDITIONS
MIN.
-
TYP. MAX. UNIT
-
60
50
1.75
-
-
K/W
K/W
K/W
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
-
-
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A; T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
Zero gate voltage drain
V
DS
= 30 V; V
GS
= 0 V;
current
T
j
= 175˚C
Gate source leakage current V
GS
=
±5
V; V
DS
= 0 V
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 40 A; V
DD
= 24 V; V
GS
= 5 V
MIN.
30
27
1
0.5
-
-
-
-
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
1.5
-
-
20
16
-
27
0.05
-
10
23
7
10
12
80
35
31
3.5
4.5
7.5
1050
270
140
-
-
2
-
2.3
24
21
45
-
10
500
100
-
-
-
20
130
60
45
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
nA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
V
DD
= 15 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 5
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
I
F
= 40 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 25 V
-
-
-
-
TYP. MAX. UNIT
-
-
0.95
1.0
52
0.08
45
180
1.2
-
-
-
A
A
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 25 A; V
DD
≤
15 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
MAX.
60
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
January 1998
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
1000
ID, Drain current (Amps)
PHP42N03LT
0.06
0.05
Drain-Source on resistance, RDS(on) (Ohms)
3V
3.5 V
4V
4.5 V
100
R
(O
DS
N
V
)=
DS
/ID
tp = 10us
100 us
1 ms
DC
10 ms
100 ms
0.04
0.03
0.02
0.01
Tj = 25 C
0
5V
10 V
VGS = 15 V
10
1
Tmb = 25 C
1
10
VDS, Drain-source voltage (Volts)
100
0
10
20
30
40
50
ID, Drain current (Amps)
PHP45N03LT
60
70
80
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth j-mb / (K/W)
D=
40
Fig.6. Typical on-state resistance
R
DS(ON)
= f(I
D
); parameter V
GS
10
7528-30
50
Drain current, ID (A)
VDS = 25 V
PHP45N03LT
1
0.5
0.2
0.1
0.1
0.05
0.02
0
0.01
1E-07
1E-05
1E-03
t/s
T
P
D
t
p
t
p
T
t
30
20
D=
10
175 C
Tj = 25 C
5
6
1E-01
1E+01
0
0
1
2
3
4
Gate-source voltage, VGS (V)
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID, Drain current (Amps)
15 V
5V
10 V
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
80
70
60
50
40
30
20
10
0
PHP45N03LT
Tj = 25 C
4.5 V
30
25
Transconductance, gfs (S)
VDS = 25 V
Tj = 25 C
PHP45N03LT
4V
20
175 C
15
10
3.5 V
3V
5
VGS = 2.5 V
0
2
4
6
8
VDS, Drain-Source voltage (Volts)
10
0
0
10
20
30
Drain current, ID (A)
40
50
Fig.5. Typical output characteristics
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance
g
fs
= f(I
D
)
January 1998
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
a
2
30V TrenchMOS
10000
C / pF
9528-30
1.5
Ciss
1
1000
0.5
Coss
Crss
0
-100
-50
0
50
Tj / C
100
150
200
100
0.1
1
VDS / V
10
100
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
min.
1
BUK959-60
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); V
GS
= 0 V; f = 1 MHz
PHP45N03LT
2.5
15
VGS, Gate-Source voltage (Volts)
VDS = 24 V
ID = 40 A
Tj = 25 C
10
5
0.5
0
-100
0
-50
0
50
Tj / C
100
150
200
0
10
20
30
Qg, Gate charge (nC)
40
50
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
IF / A
9528-30
1E-01
60
50
40
1E-02
2%
typ
98%
1E-03
Tj / C = 175
25
30
1E-04
20
10
0
1E-05
1E-05
0
0.5
0
0.5
1
1.5
2
2.5
3
1
VSDS / V
1.5
2
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
)
January 1998
5
Rev 1.300