EEWORLDEEWORLDEEWORLD

Part Number

Search

EP20K1000CF1020I-8

Description
Loadable PLD, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,90 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

EP20K1000CF1020I-8 Overview

Loadable PLD, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020

EP20K1000CF1020I-8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codeBGA
package instructionHBGA, BGA1020,32X32,40
Contacts1020
Reach Compliance Codecompli
ECCN code3A001.A.7.A
JESD-30 codeS-PBGA-B1020
JESD-609 codee0
length33 mm
Humidity sensitivity level3
Dedicated input times4
Number of I/O lines708
Number of entries700
Number of logical units38400
Output times700
Number of terminals1020
organize4 DEDICATED INPUTS, 708 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeHBGA
Encapsulate equivalent codeBGA1020,32X32,40
Package shapeSQUARE
Package formGRID ARRAY, HEAT SINK/SLUG
power supply1.8,1.8/3.3 V
Programmable logic typeLOADABLE PLD
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width33 mm
APEX 20KC
®
Programmable Logic
Device
Data Sheet
April 2001, ver. 1.1
Features...
I
Preliminary
Information
I
Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process
– 25 to 35% faster design performance than APEX
TM
20KE devices
– Pin-compatible with APEX 20KE devices
– High-performance, low-power copper interconnect
– MultiCore
TM
architecture integrating look-up table (LUT) logic
and embedded memory
LUT logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
High-density architecture
100,000 to 1.5 million typical gates (see
Table 1)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Note (1)
EP20K400C
1,052,000
400,000
16,640
104
212,992
4
-7, -8, -9
1,664
488
Table 1. APEX 20KC Device Features
Feature
Maximum
system gates
Typical gates
LEs
ESBs
Maximum RAM
bits
PLLs
(2)
Speed grades
(3)
Maximum
macrocells
Maximum user
I/O pins
Notes:
(1)
(2)
(3)
EP20K100C
263,000
100,000
4,160
26
53,248
2
-7, -8, -9
416
246
EP20K200C
526,000
200,000
8,320
52
106,496
2
-7, -8, -9
832
376
EP20K600C
1,537,000
600,000
24,320
152
311,296
4
-7, -8, -9
2,432
588
EP20K1000C
1,772,000
1,000,000
38,400
160
327,680
4
-7, -8, -9
2,560
708
EP20K1500C
2,392,000
1,500,000
51,840
216
442,368
4
-7, -8, -9
3,456
808
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
Altera Corporation
A-DS-APEX20KC-01.1
1
Half the size, twice the power! - Gallium nitride technology revolutionizes robotics, renewable energy, telecommunications and more
[align=left][color=rgb(85, 85, 85)][font="][size=14px][color=rgb(170, 102, 102)][url=https://e2echina.ti.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-0 0-01-15/4645.102418_5F0...
alan000345 TI Technology Forum
Capsizing in the gutter - copper pouring is risky
I was in a rush to deliver goods. I didn’t have time for the sample. I just made a small batch and poured copper. I made a mistake in a hurry. The ground terminal of the Kelvin sampling was poured. Wh...
PowerAnts PCB Design
Low-power MCU optimizes battery-powered system design
[size=4]For embedded systems, especially battery-powered systems (such as portable electronic devices, metering applications, and medical devices), reducing system power consumption and extending batt...
fish001 Microcontroller MCU
SMT reflow oven temperature process curve setting
[align=left][color=rgb(51, 51, 51)][font=-apple-system-font, BlinkMacSystemFont, "][size=17px] With the advancement of science and technology and the improvement of people's living standards, people's...
ohahaha PCB Design
Share an OCR software
[i=s]This post was last edited by lehuijie on 2018-9-6 13:17[/i] This is a PC software. I will put it in this section first. If it is wrong, the moderator will remove it! This is a free OCR software. ...
lehuijie Download Centre
The list of national competitions has been released. Have you bought all the equipment?
The national competition list is out. Friends who don’t know it yet can check it out here: https://en.eeworld.com/bbs/thread-1084541-1-1.html As soon as the list came out, everyone started to guess th...
okhxyyo Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号