S34ML01G1
S34ML02G1
S34ML04G1
1Gb, 2 Gb, 4 Gb, 3 V, 1-bit ECC, SLC NAND
Flash Memory for Embedded
Distinctive Characteristics
■
for Embedded
■
Density
❐
1 Gb/ 2 Gb / 4 Gb
Architecture
❐
Input / Output Bus Width: 8-bits / 16-bits
❐
Page size:
• x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
• x16 = 1056 (1024 + 32) words; 32 words is spare area
❐
Block size: 64 Pages
• x8 = 128 KB + 4 KB
• x16 = 64k + 2k words
❐
Plane size:
• 1
Gb
/ 2
Gb
: 1024 Blocks per Plane
x8 = 128 MB + 4 MB
x16 = 64M + 2M words
• 4
Gb
: 2048 Blocks per Plane
x8 = 256 MB+ 8 MB
x16 = 128M + 4M words
❐
Device size:
• 1
Gb
: 1 Plane per Device or 128 MB
• 2
Gb
: 2 Planes per Device or 256 MB
• 4
Gb
: 2 Planes per Device or 512 MB
■
NAND flash interface
❐
Open NAND Flash Interface (ONFI) 1.0 compliant
❐
Address, Data and Commands multiplexed
Supply voltage
❐
3.3-V device: Vcc = 2.7 V ~ 3.6 V
Security
❐
One Time Programmable (OTP) area
❐
Hardware program/erase disabled during power transition
Additional features
❐
2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
❐
Supports Copy Back Program
❐
2 Gb and 4 Gb parts support Multiplane Copy Back Program
❐
Supports Read Cache
Electronic signature
❐
Manufacturer ID: 01h
Operating temperature
❐
Industrial: -40 °C to 85 °C
❐
Automotive: -40 °C to 105 °C
■
■
■
■
■
Performance
■
Page Read / Program
❐
Random access: 25 µs (Max)
❐
Sequential access: 25 ns (Min)
❐
Program time / Multiplane Program time: 200 µs (Typ)
Block Erase (S34ML01G1)
❐
Block Erase time: 2.0 ms (Typ)
Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)
❐
Block Erase time: 3.5 ms (Typ)
Reliability
❐
100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
❐
10 Year Data retention (Typ)
■
For one plane structure (1-Gb density)
• Block zero is valid and will be valid for at least 1,000
program-erase cycles with ECC
❐
For two plane structures (2-Gb and 4-Gb densities)
• Blocks zero and one are valid and will be valid for at least
1,000 program-erase cycles with ECC
❐
■
■
■
Package options
❐
Lead Free and Low Halogen
❐
48-Pin TSOP 12
20
1.2 mm
❐
63-Ball BGA 9
11
1 mm
SkyHigh Memory Limited
Document Number: 002-00676 Rev. *W
Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com
Revised May 03, 2019
S34ML01G1
S34ML02G1
S34ML04G1
Contents
1.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.
2.1
2.2
2.3
2.4
2.5
2.6
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
4.
4.1
4.2
4.3
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
General Description.....................................................
4
Logic Diagram................................................................ 5
Connection Diagram ...................................................... 6
Pin Description............................................................... 7
Block Diagram................................................................ 8
Array Organization ......................................................... 9
Addressing ................................................................... 10
Mode Selection ............................................................ 12
Bus Operation
............................................................
Command Input ...........................................................
Address Input...............................................................
Data Input ....................................................................
Data Output..................................................................
Write Protect ................................................................
Standby........................................................................
Command Set.............................................................
Page Read ...................................................................
Page Program..............................................................
Multiplane Program
— S34ML02G1 and S34ML04G1 ................................
Page Reprogram
— S34ML02G1 and S34ML04G1 ................................
Block Erase..................................................................
Multiplane Block Erase
— S34ML02G1 and S34ML04G1 ................................
Copy Back Program.....................................................
EDC Operation — S34ML02G1 and S34ML04G1.......
Read Status Register...................................................
Read Status Enhanced
— S34ML02G1 and S34ML04G1 ................................
Read Status Register Field Definition ..........................
Reset............................................................................
Read Cache .................................................................
Cache Program............................................................
Multiplane Cache Program
— S34ML02G1 and S34ML04G1 ................................
Read ID........................................................................
Read ID2......................................................................
Read ONFI Signature ..................................................
Read Parameter Page .................................................
One-Time Programmable (OTP) Entry ........................
Signal Descriptions
...................................................
Data Protection and Power On / Off Sequence ...........
Ready/Busy..................................................................
Write Protect Operation ...............................................
Electrical Characteristics
..........................................
Valid Blocks .................................................................
Absolute Maximum Ratings .........................................
Recommended Operating Conditions..........................
AC Test Conditions ......................................................
AC Characteristics .......................................................
DC Characteristics .......................................................
Pin Capacitance...........................................................
13
13
13
13
13
13
13
14
15
15
16
16
18
18
18
19
21
22
22
22
23
24
25
26
29
29
29
31
32
32
32
33
34
34
34
34
34
35
36
36
5.8
5.9
6.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
7.
7.1
8.
9.
9.1
9.2
10.
11.
Thermal Resistance ...................................................... 37
Program / Erase Characteristics ................................... 37
Timing Diagrams
......................................................... 38
Command Latch Cycle.................................................. 38
Address Latch Cycle ..................................................... 38
Data Input Cycle Timing................................................ 39
Data Output Cycle Timing
(CLE=L, WE#=H, ALE=L, WP#=H)............................... 39
Data Output Cycle Timing
(EDO Type, CLE=L, WE#=H, ALE=L) .......................... 40
Page Read Operation ................................................... 40
Page Read Operation (Interrupted by CE#).................. 41
Page Read Operation Timing with CE# Don’t Care...... 41
Page Program Operation .............................................. 42
Page Program Operation Timing
with CE# Don’t Care ..................................................... 42
Page Program Operation with Random Data Input ...... 43
Random Data Output In a Page ................................... 43
Multiplane Page Program Operation
— S34ML02G1 and S34ML04G1 ................................. 44
Block Erase Operation .................................................. 45
Multiplane Block Erase
— S34ML02G1 and S34ML04G1 ................................. 45
Copy Back Read with Optional Data Readout .............. 46
Copy Back Program Operation
With Random Data Input............................................... 46
Multiplane Copy Back Program
— S34ML02G1 and S34ML04G1 ................................. 47
Read Status Register Timing ........................................ 48
Read Status Enhanced Timing ..................................... 48
Reset Operation Timing ................................................ 48
Read Cache .................................................................. 49
Cache Program............................................................. 50
Multiplane Cache Program
— S34ML02G1 and S34ML04G1 ................................. 51
Read ID Operation Timing ............................................ 53
Read ID2 Operation Timing .......................................... 53
Read ONFI Signature Timing........................................ 54
Read Parameter Page Timing ...................................... 54
OTP Entry Timing ......................................................... 54
Power On and Data Protection Timing ......................... 55
WP# Handling............................................................... 55
Physical Interface
....................................................... 56
Physical Diagram .......................................................... 56
System Interface
......................................................... 58
Error Management
...................................................... 59
System Bad Block Replacement................................... 59
Bad Block Management................................................ 60
Ordering Information
.................................................. 61
Document History Page
............................................. 62
Document Number: 002-00676 Rev. *W
Page 2 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Sales, Solutions, and Legal Information .......................... 71
Worldwide Sales and Design Support ........................... 71
Products ........................................................................ 71
PSoC® Solutions ........................................................... 71
Cypress Developer Community ..................................... 71
Technical Support ......................................................... 71
Document Number: 002-00676 Rev. *W
Page 3 of 70
S34ML01G1
S34ML02G1
S34ML04G1
1. General Description
The Cypress S34ML01G1, S34ML02G1, and S34ML04G1 series is offered with a 3.3-V V
CC
power supply, and with ×8 or ×16 I/O
interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into
blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for ×8 is
(2048 + 64 spare) bytes; for ×16 (1024 + 32) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (×8), or 1056 words (×16) in 200 µs
and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (×8) or 64-kword block (×16). In
addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a
time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by
50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (×8) or 256
words (×16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back
operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram
re-programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the
second plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during
re-program operations.
Note:
The S34ML01G1 device does not support EDC.
Document Number: 002-00676 Rev. *W
Page 4 of 70
S34ML01G1
S34ML02G1
S34ML04G1
The devices come with an OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be
stored permanently. This security feature is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the
data sheet. For more details, contact your nearest Cypress sales office.
Table 1. Product List
Device
S34ML01G1
S34ML02G1
S34ML04G1
Density (bits)
Main
128M x 8
64M x 16
256M x 8
128M x 16
512M x 8
256M x 16
Spare
4M x 8
2M x 16
8M x 8
4M x 16
16M x 8
8M x 16
Number of Planes
1
2
2
Number of Blocks
per Plane
1024
1024
2048
EDC Support
No
Yes
Yes
1.1
Logic Diagram
Figure 1. Logic Diagram
VCC
CE#
WE#
RE#
ALE
CLE
WP#
I/O0~I/O7
R/B#
VSS
Table 2. Signal Names
Signal
I/O7 - I/O0
(×8)
I/O8 - I/O15
(×16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Description
Data Input / Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
Document Number: 002-00676 Rev. *W
Page 5 of 70
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