XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
JULY 2012
REV. 1.1.0
GENERAL DESCRIPTION
The XR20M1170
1
(M1170) is a high performance
universal asynchronous receiver and transmitter
(UART) with 64 byte TX and RX FIFOs and a
selectable I
2
C/SPI slave interface. The M1170
operates from 1.62 to 3.63 volts. The enhanced
features in the M1170 include a programmable
fractional baud rate generator, an 8X and 4X
sampling rate that allows for a maximum baud rate of
16 Mbps at 3.3V. The standard features include 16
selectable TX and RX FIFO trigger levels, automatic
hardware (RTS/CTS) and software (Xon/Xoff) flow
control, and a complete modem interface. Onboard
registers provide the user with operational status and
data error flags. An internal loopback capability
allows system diagnostics. The M1170 is available in
the 24-pin QFN, 16-pin QFN, 24-pin TSSOP and 16-
pin TSSOP packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
1.62 to 3.6 Volt Operation
•
Selectable I
2
C/SPI Interface
•
SPI clock frequency up to
■
■
■
18 MHz at 3.3 V
16 MHz at 2.5 V
8 MHz at 1.8 V
Data rate of up to
16 Mbps at 3.3 V
Data rate of up to
12.5 Mbps at 2.5 V
Data rate of up to
8 Mbps at 1.8 V
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 64 bytes
16 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Halt and Resume Transmission Control
Automatic RS-485 Half-duplex
Control Output via RTS#
Direction
•
Full-featured UART
■
■
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Battery-Operated Devices
•
Cellular Data Devices
•
Factory Automation and Process Controls
■
Wireless Infrared (IrDA 1.0 and 1.1) Encoder/
Decoder
Automatic sleep mode (< 15 uA at 3.3V)
General Purpose I/Os
Full modem interface
■
■
■
•
Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
•
24-QFN,
packages
F
IGURE
1. XR20M1170 B
LOCK
D
IAGRAM
16-QFN,
24-TSSOP,
16-TSSOP
VCC
1.62V – 3.63V
64 Byte
TX FIFO
UART
Regs
64 Byte
RX FIFO
TX
RX
RTS#
CTS#
IRQ#
SDA
SCL
A0/CS#
A1/SI
SO
I2C/SPI#
I
2
C/SPI
Interface
GPIOs
BRG
Crystal Osc/Buffer
GPIO[7:0]
XTAL1
XTAL2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
REV. 1.1.0
GPIO4/DSR#
GPIO5/DTR#
RESET#
VCC 1
RTS#
IRQ#
SCL
24 GPIO7/RI#
23 GPIO6/CD#
22 CTS#
21 RESET#
20 GPIO4/DSR#
24-Pin
TSSOP
19 GPIO5/DTR#
18 RTS#
17 IRQ#
16 SCL
15 SDA
14 GND
13 GPIO3
A0/CS# 2
A1/SI
S DA
GND
G PIO 3
X TAL2
X TAL1
G PIO 2
3
18 17 16 15 14 13
C TS# 19
12
G PIO 6/C D# 20
11
G PIO 7/R I# 21
VC C 22
A0/C S# 23
A1/SI 24
1
SO
2
GPIO0
3
GPIO1
4
I2C/SPI#
5
RX
6
TX
24-Pin Q FN
10
9
8
7
SO 4
GPIO0 5
GPIO1 6
I2C/SPI#
7
RX 8
TX 9
GPIO2 10
XTAL1 11
XTAL2 12
RESET#
RTS#
IRQ#
SCL
A0/CS# 1
A1/SI 2
SO 3
I2C/SPI# 4
RX 5
TX 6
XTAL1 7
XTAL2 8
16-Pin
TSSOP
16 VCC
15 CTS#
14 RESET#
13 RTS#
12 IRQ#
11 SCL
10 SDA
9 GND
12 11 10 9
CTS# 13
8 SDA
7 GND
VCC 14 16-Pin
QFN
6 XTAL2
A0/CS# 15
5 XTAL1
A1/SI 16
1 2 3 4
SO
I2C/SPI#
RX
TX
ORDERING INFORMATION
P
ART
N
UMBER
XR20M1170IL24-F
XR20M1170IL24TR-F
XR20M1170IL16-F
XR20M1170IL16TR-F
XR20M1170IG24-F
XR20M1170IG24TR-F
XR20M1170IG16-F
XR20M1170IG16TR-F
P
ACKAGE
24-pin QFN
24-pin QFN
16-pin QFN
16-pin QFN
24-Lead TSSOP
24-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
Active
Active
Active
N
OTE
:
TR = Tape and Reel, F = Green / RoHS
2
XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
24-QFN
P
IN
#
16-QFN
P
IN
#
24-TSSOP 16-TSSOP
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
I2C (SPI) INTERFACE
GPIO0
GPIO1
I2C/SPI#
2
3
4
-
-
2
5
6
7
-
-
4
I/O
I/O
I/O
General purpose I/O pin.
General purpose I/O pin.
I
2
C-bus or SPI interface select. I
2
C-bus interface
is selected if this pin is HIGH. SPI interface is
selected if this pin is LOW
UART Receive Data or Infrared Receive Data.
UART receive data input must idle HIGH. Infrared
receive data input must idle LOW. If this pin is not
used, tie it to VCC or pull it high via a 100k ohm
resistor.
UART Transmit Data or Infrared Encoder Data. In
the standard UART Transmit Data mode, the TX
signal will be HIGH during reset or idle (no data). In
the Infrared mode, the inactive state (no data) for
the Infrared encoder/decoder interface is LOW. If
ithis pin is not used, it should be left unconnected.
General purpose I/O pin.
Crystal or external clock input.
Crystal or buffered clock output.
General purpose I/O pin.
Power supply common, ground.
I
2
C-bus data input/output (open-drain). If SPI con-
figuration is selected, then this pin is undefined and
must be connected to VCC.
I
2
C-bus or SPI serial input clock.
When the I
2
C-bus interface is selected, the serial
clock idles HIGH. When the SPI interface is
selected, the serial clock idles LOW.
IRQ#
RTS#
14
15
10
11
17
18
12
13
OD
O
Interrupt output (open-drain, active LOW).
UART Request-To-Send. This output can be used
for Auto RTS Hardware Flow Control, Auto RS-485
Half-Duplex direction control or as a general pur-
pose output.
General purpose I/O pin or DTR# output.
General purpose I/O pin or DSR# input.
RX
5
3
8
5
I
TX
6
4
9
6
O
GPIO2
XTAL1
XTAL2
GPIO3
GND
SDA
7
8
9
10
11
12
-
5
6
-
7
8
10
11
12
13
14
15
-
7
8
-
9
10
I/O
I
O
I/O
Pwr
O
SCL
13
9
16
11
I
GPIO5
DTR#
GPIO4
DSR#
16
17
-
-
19
20
-
-
I/O
I/O
3
XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
Pin Description
N
AME
RESET#
24-QFN
P
IN
#
18
16-QFN
P
IN
#
12
24-TSSOP 16-TSSOP
T
YPE
P
IN
#
P
IN
#
21
14
I
D
ESCRIPTION
Reset (active LOW) - A longer than 40 ns LOW
pulse on this pin will reset the internal registers and
all outputs. The UART transmitter output will be
idle and the receiver input will be ignored.
UART Clear-To-Send. This input can be used for
Auto CTS Hardware Flow Control or as a general
purpose input.
General purpose I/O pin or CD# input.
General purpose I/O pin or RI# input.
1.62V to 3.6V power supply.
I
2
C-bus device address select A0 or SPI chip
select. If I
2
C-bus configuration is selected, this pin
along with the A1 pin allows user to change the
device’s base address. If SPI configuration is
selected, this pin is the SPI chip select pin
(Schmitt-trigger, active LOW).
I
2
C-bus device address select A1 or SPI data input
pin. If I
2
C-bus onfiguration is selected, this pin
along with A0 pin allows user to change the
device’s base address. If SPI configuration is
selected, this pin is the SPI data input pin.
SPI data output pin. If SPI configuration is
selected then this pin is a three-stateable output
pin. If I2C-bus configuration is selected, this pin is
undefined and must be left unconnected.
The center pad on the backside of the QFN pack-
ages is metallic and is not electrically connected to
anything inside the device. It must be soldered on
to the PCB and may be optionally connected to
GND on the PCB. The thermal pad size on the
PCB should be the approximate size of this center
pad and should be solder mask defined. The sol-
der mask opening should be at least 0.0025"
inwards from the edge of the PCB thermal pad.
No Connection.
REV. 1.1.0
CTS#
19
13
22
15
I
GPIO6
CD#
GPIO7
RI#
VCC
A0
CS#
20
21
22
23
-
-
14
15
23
24
1
2
-
-
16
1
I/O
I/O
Pwr
I
A1
SI
24
16
3
2
I
SO
1
1
4
3
O
-
PAD
PAD
-
-
Pwr
NC
-
-
-
-
-
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
4
XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR20M1170 (M1170) integrates a selectable I
2
C/SPI bus interface with an enhanced Universal
Asynchronous Receiver and Transmitter (UART). The configuration registers set is 16550 UART compatible
for control, status and data transfer. Additionally, the M1170 has 64-bytes of transmit and receive FIFOs,
automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, infrared encoder and decoder (IrDA 1.0 and 1.1),
programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps
with 4X sampling clock rate. The XR20M1170 is a 1.62V to 3.63V device. The M1170 is fabricated with an
advanced CMOS process.
Enhanced Features
The M1170 UART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the industry standard 16C550. The M1170 is designed to work with low supply voltage and high
performance data communication systems, that require fast data processing time. Increased performance is
realized in the M1170 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow
control mechanism. This allows the external processor to handle more networking tasks within a given time.
For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the M1170, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
The M1170 supports a half-duplex output direction control signaling pin, RTS#, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set EFCR bit-4 to “1”. This pin is HIGH for receive state and LOW for transmit state. The polarity of the
RTS# pin can be inverted via EFCR bit-5.
Data Rate
The M1170 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate, and 4 Mbps at 3.3V with 16X internal sampling clock rate. The device can operate
with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for
data rates of up to 3.68 Mbps.
The rich feature set of the M1170 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the M1170 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C2550.
5
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