C8051F70x/71x
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
10-Bit ADC
•
Up to 500 ksps
•
Up to 16 external single-ended inputs
•
VREF from on-chip VREF, external pin or V
DD
•
Internal or external start of conversion source
•
Built-in temperature sensor
-
Comparator
•
Programmable hysteresis and response time
•
Configurable as interrupt or reset source
Capacitive Sense Interface
-
16-bit precision measurement
-
Up to 32 channels
-
Auto-scan and compare
-
Auto-accumulate 4x, 8x, and 16x samples
-
High conversion speed (40 µs per input)
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost,
complete
development kit
Memory
-
512 bytes internal data RAM (256 + 256)
-
Up to 16 kB Flash; In-system programmable in 512-
-
Digital Peripherals
-
Up to 54 Port I/O with high sink current
-
Hardware enhanced UART, SMBus™ (I
2
C compati-
-
-
ble), and enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with 3
capture/compare modules and enhanced PWM
functionality
Real time clock mode using timer and crystal
byte Sectors
Up to 32-byte data EEPROM
-
Clock Sources
-
24.5 MHz ±2% Oscillator
•
Supports crystal-less UART operation
-
External oscillator: Crystal, RC, C, or clock
-
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
-
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
Supply Voltage 1.8 to 3.6 V
-
Built-in voltage supply monitor
64-Pin TQFP, 48-Pin TQFP, 48-Pin QFN
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
CROSSBAR
Ext. Memory I/F
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6.0
– 6.5
10-bit
500 ksps
ADC
Capacitive
Sense
TEMP
SENSOR
+
–
VOLTAGE
COMPARATOR
24.5 MHz PRECISION INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
512 B RAM
32 B EEPROM
POR
WDT
Rev. 0.3 10/09
Copyright © 2009 by Silicon Laboratories
C8051F70x/71x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F70x/71x
Table of Contents
1. System Overview ..................................................................................................... 17
2. Ordering Information ............................................................................................... 24
3. Pin Definitions.......................................................................................................... 26
4. TQFP-64 Package Specifications ........................................................................... 33
5. TQFP-48 Package Specifications ........................................................................... 35
6. QFN-48 Package Specifications ............................................................................. 37
7. Electrical Characteristics ........................................................................................ 39
7.1. Absolute Maximum Specifications..................................................................... 39
7.2. Electrical Characteristics ................................................................................... 40
8. 10-Bit ADC (ADC0, C8051F700/2/4/6/8 and C8051F710/2/4 only)......................... 46
8.1. Output Code Formatting .................................................................................... 47
8.2. 8-Bit Mode ......................................................................................................... 47
8.3. Modes of Operation ........................................................................................... 47
8.3.1. Starting a Conversion................................................................................ 47
8.3.2. Tracking Modes......................................................................................... 48
8.3.3. Settling Time Requirements...................................................................... 49
8.4. Programmable Window Detector....................................................................... 53
8.4.1. Window Detector Example........................................................................ 55
8.5. ADC0 Analog Multiplexer .................................................................................. 56
9. Temperature Sensor (C8051F700/2/4/6/8 and C8051F710/2/4 only) .................... 58
9.1. Calibration ......................................................................................................... 58
10. Voltage and Ground Reference Options.............................................................. 60
10.1. External Voltage References........................................................................... 61
10.2. Internal Voltage Reference Options ................................................................ 61
10.3. Analog Ground Reference............................................................................... 61
10.4. Temperature Sensor Enable ........................................................................... 61
11. Voltage Regulator (REG0) ..................................................................................... 63
12. Comparator0........................................................................................................... 65
12.1. Comparator Multiplexer ................................................................................... 70
13. Capacitive Sense (CS0) ......................................................................................... 72
13.1. Configuring Port Pins as Capacitive Sense Inputs .......................................... 73
13.2. Capacitive Sense Start-Of-Conversion Sources ............................................. 73
13.3. Automatic Scanning......................................................................................... 73
13.4. CS0 Comparator.............................................................................................. 74
13.5. CS0 Conversion Accumulator ......................................................................... 75
13.6. Capacitive Sense Multiplexer .......................................................................... 81
14. CIP-51 Microcontroller........................................................................................... 83
14.1. Instruction Set.................................................................................................. 84
14.1.1. Instruction and CPU Timing .................................................................... 84
14.2. CIP-51 Register Descriptions .......................................................................... 89
15. Memory Organization ............................................................................................ 93
15.1. Program Memory............................................................................................. 94
15.1.1. MOVX Instruction and Program Memory ................................................ 94
Rev. 0.3
3
C8051F70x/71x
15.2. EEPROM Memory ........................................................................................... 94
15.3. Data Memory ................................................................................................... 94
15.3.1. Internal RAM ........................................................................................... 94
15.3.1.1. General Purpose Registers ............................................................ 95
15.3.1.2. Bit Addressable Locations .............................................................. 95
15.3.1.3. Stack............................................................................................... 95
16. External Data Memory Interface and On-Chip XRAM ......................................... 96
16.1. Accessing XRAM............................................................................................. 96
16.1.1. 16-Bit MOVX Example ............................................................................ 96
16.1.2. 8-Bit MOVX Example .............................................................................. 96
16.2. Configuring the External Memory Interface ..................................................... 97
16.3. Port Configuration............................................................................................ 97
16.4. Multiplexed and Non-multiplexed Selection................................................... 100
16.4.1. Multiplexed Configuration...................................................................... 100
16.4.2. Non-multiplexed Configuration.............................................................. 101
16.5. Memory Mode Selection................................................................................ 102
16.5.1. Internal XRAM Only .............................................................................. 102
16.5.2. Split Mode without Bank Select............................................................. 102
16.5.3. Split Mode with Bank Select.................................................................. 103
16.5.4. External Only......................................................................................... 103
16.6. Timing............................................................................................................ 103
16.6.1. Non-Multiplexed Mode .......................................................................... 105
16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 105
16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 106
16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 107
16.6.2. Multiplexed Mode .................................................................................. 108
16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 108
16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 109
16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 110
17. In-System Device Identification.......................................................................... 113
18. Special Function Registers................................................................................. 115
19. Interrupts .............................................................................................................. 122
19.1. MCU Interrupt Sources and Vectors.............................................................. 123
19.1.1. Interrupt Priorities.................................................................................. 123
19.1.2. Interrupt Latency ................................................................................... 123
19.2. Interrupt Register Descriptions ...................................................................... 124
19.3. INT0 and INT1 External Interrupts................................................................. 131
20. Flash Memory....................................................................................................... 133
20.1. Programming The Flash Memory .................................................................. 133
20.1.1. Flash Lock and Key Functions .............................................................. 133
20.1.2. Flash Erase Procedure ......................................................................... 133
20.1.3. Flash Write Procedure .......................................................................... 134
20.2. Non-volatile Data Storage ............................................................................. 134
20.3. Security Options ............................................................................................ 134
20.4. Flash Write and Erase Guidelines ................................................................. 135
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C8051F70x/71x
20.4.1. VDD Maintenance and the VDD Monitor .............................................. 136
20.4.2. PSWE Maintenance .............................................................................. 136
20.4.3. System Clock ........................................................................................ 137
21. EEPROM ............................................................................................................... 140
21.1. RAM Reads and Writes ................................................................................. 140
21.2. Auto Increment .............................................................................................. 140
21.3. Interfacing with the EEPROM........................................................................ 140
21.4. EEPROM Security ......................................................................................... 141
22. Power Management Modes................................................................................. 145
22.1. Idle Mode....................................................................................................... 145
22.2. Stop Mode ..................................................................................................... 146
22.3. Suspend Mode .............................................................................................. 146
23. Reset Sources ...................................................................................................... 148
23.1. Power-On Reset ............................................................................................ 149
23.2. Power-Fail Reset / VDD Monitor ................................................................... 150
23.3. External Reset ............................................................................................... 151
23.4. Missing Clock Detector Reset ....................................................................... 151
23.5. Comparator0 Reset ....................................................................................... 152
23.6. Watchdog Timer Reset.................................................................................. 152
23.7. Flash Error Reset .......................................................................................... 152
23.8. Software Reset .............................................................................................. 152
24. Watchdog Timer................................................................................................... 154
24.1. Enable/Reset WDT........................................................................................ 154
24.2. Disable WDT ................................................................................................. 154
24.3. Disable WDT Lockout.................................................................................... 154
24.4. Setting WDT Interval ..................................................................................... 154
25. Oscillators and Clock Selection ......................................................................... 156
25.1. System Clock Selection................................................................................. 156
25.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 158
25.3. External Oscillator Drive Circuit..................................................................... 160
25.3.1. External Crystal Example...................................................................... 162
25.3.2. External RC Example............................................................................ 163
25.3.3. External Capacitor Example.................................................................. 164
26. Port Input/Output ................................................................................................. 165
26.1. Port I/O Modes of Operation.......................................................................... 166
26.1.1. Port Pins Configured for Analog I/O...................................................... 166
26.1.2. Port Pins Configured For Digital I/O...................................................... 166
26.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 167
26.1.4. Increasing Port I/O Drive Strength ........................................................ 168
26.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 168
26.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 168
26.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 169
26.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 169
26.3. Priority Crossbar Decoder ............................................................................. 170
26.4. Port I/O Initialization ...................................................................................... 172
Rev. 0.3
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