TC59YM816BKG24A,32A,32B,40B,32C,40C
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
Lead Free
OVERVIEW
The Rambus XDR
TM
DRAM device is a general purpose high-performance memory device suitable for use in a
broad range of applications including computer memory, graphics, video, and any other application where high
bandwidth and low latency are required.
The 256Mb Rambus XDR DRAM device is a CMOS DRAM organized as 16M words by 16 bits. The use of
Differential Rambus Signaling Level (DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using
conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly
addressed memory transactions. The highly efficient protocol yields over 95% utilization while allowing fine access
granularity. The device's 8 banks support up to four interleaved transactions.
FEATURES
•
Highest pin bandwidth available
−
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
−
Bi-directional differential RSL (DRSL)
Flexible read/write bandwidth allocation
Minimum pin count
−
Programmable on-chip termination
Adaptive impedance matching
Reduced system cost and routing complexity
•
Highest sustained bandwidth per DRAM device
−
−
−
−
−
•
8000/6400/4800 MB/s sustained data rate
8 banks: bank-interleaved transactions at full bandwidth
Dynamic request scheduling
Early-Read-after-Write support for maximum efficiency
Zero overhead refresh
Low latency
−
2.0/2.5/3.33 ns request packets
−
Point-to-point data interconnect for fastest possible flight time
−
Support for low-latency, fast-cycle cores
•
Low power
−
−
−
−
−
1.8V V
DD
Programmable small-swing I/O signaling (DRSL)
Low power PLL/DLL design
Power Down Self Refresh support
Per pin I/O Power Down for narrow-width operation
•
Programmable I/O width
− ×4
/
×8
/
×16
programmable device I/O width
Note: XDR is a trademark or a registered trademark in Japan and/or other countries.
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2004-11-15
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TC59YM816BKG24A,32A,32B,40B,32C,40C
PIN ASSIGNMENT (TOP VIEW)
XDR DRAM CSP x16
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
V
DD
DQN7
VTERM
K
DQN9
J
V
DD
V
DD
V
DD
GND
VTERM
H
GND
G
V
DD
F
E
GND
D
V
DD
C
SDI
GND
B
DQN8
A
DQN2
DQN3
DQ3
DQN15
DQ9
DQN5
DQ8
DQN4
DQ2
DQN14
RQ10
RQ11
CFM
CFMN
RSRV
RQ4
RQ3
RQ0
GND
VTERM
DQ15
DQ5
V
DD
GND
RSRV
DQ4
V
DD
GND
DQ14
V
DD
GND
V
DD
GND
GND
GND
V
DD
V
DD
V
DD
GND
VTERM
VTERM
GND
GND
V
DD
CMD
SCK
GND
GND
V
DD
GND
V
DD
GND
V
DD
GND
GND
VTERM
GND
V
DD
DQN6
GND
DQN13
GND
DQN12
RQ9
RQ8
RQ7
RQ6
VREF
RQ1
RQ2
V
DD
GND
RST
DQ7
DQN11
DQ13
RQ5
DQ12
DQ6
DQN10
DQN1
DQN0
DQ11
DQ1
V
DD
V
DD
GND
V
DD
SDO
DQ0
DQ10
Note:
•
•
•
•
•
: Optional ball / Depopulated
: Depopulated
RSRV: Reserved pin
DQ8…DQ15, DQN8…DQN15 are RSRV’s for
×8
DQ4…DQ15, DQN4…DQN15 are RSRV’s for
×4
Key Timing Parameters/Part Numbers
Organization
a
Bandwidth (1/t
BIT
)
2400
3200
3200
3200
4000
4000
b
Latency (t
RAC
)
36
27
35
35
28
28
c
Bin
A
A
B
C
B
C
d
Part Number
TC59YM816BKG24A
TC59YM816BKG32A
TC59YM816BKG32B
TC59YM816BKG32C
TC59YM816BKG40B
TC59YM816BKG40C
8
×
2K
×
1K
×
16
8
×
2K
×
1K
×
16
8
×
2K
×
1K
×
16
8
×
2K
×
1K
×
16
8
×
2K
×
1K
×
16
8
×
2K
×
1K
×
16
a. Bank
×
Row
×
Column
×
Width
b. Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 60 and “Timing Characteristics” on page
62. Note that t
BIT
=
t
CYCLE
/ 8.
c. Read access time t
RAC
(=t
RCD−R
+
t
CAC
) measured in ns. See “Timing Parameters” on page 63.
d. Timing parameter bin. See “Timing Parameters” on page 63. This is a measure of the number of interleaved read transactions
needed for maximum efficiency (the value Ceiling (t
RC-R
/t
RR-D
).
For bin A, t
RC−A
/ t
RR−D
=
4, and for bin B, t
RC−R
/ t
RR−D
=
5
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2004-11-15
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TC59YM816BKG24A,32A,32B,40B,32C,40C
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets
of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11…RQ0 request pins, and
DQ15…DQ0/DQN15...DQN0 data pins. The “N” appended to a signal name denotes the complementary signal of a
differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on
the signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus
uses a set of 2 bit-windows on each signal, while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T
0
contains an activate
(ACT) command. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array
for the bank. A second request packet at clock edge T
1
contains a write (WR) command. This causes the data packet
D (a1) at edge T
4
to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock
edge T
3
contains another write (WR) command. This causes the data packet D (a2) at edge T
6
to be also be written
to column Ca2. A final request packet at clock edge T
13
contains a precharge (PRE) command.
The spacing between the request packets are constrained by the following timing parameters in the diagram:
t
RCD-W
, t
CC
, and t
WRP
. In addition, the spacing between the request packets and data packets are constrained by
the t
CWRD
parameter. The spacing of the CFM/CFMN clock edges is constrained by t
CYCLE
.
Figure 1.
T
0
CFM
CFMN
XDR DRAM Device Write and Read Transactions
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
CYCLE
RQ11 ACT WR
a1
…RQ0 a0
t
RCD-W
DQ15…0
DQN15…0
t
CWD
t
CC
D(a1)
WR
a2
t
WRP
D(a2)
PRE
a3
Transaction a: WR
a0
=
{Ba, Ra}
a1
=
{Ba, Ca1}
a2
=
{Ba, Ca2}
a3
=
{Ba}
Write Transaction
T
0
CFM
CFMN
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
CYCLE
RQ11 ACT
…RQ0 a0
t
RCD-R
DQ15…0
DQN15…0
t
CAC
RD
a1
t
CC
RD
a2
t
RDP
Q(a1)
Q(a2)
PRE
a3
Transaction a: RD
a0
=
{Ba, Ra}
a1
=
{Ba, Ca1}
a2
=
{Ba, Ca2}
a3
=
{Ba}
Read Transaction
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of
bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock
edge T
5
contains a read (RD) command. This causes the data packet Q (a1) at edge T
11
to be read from column Ca1
of the sense amp array for bank Ba. A third request packet at clock edge T
7
contains another RD command. This
causes the data packet Q (a2) at edge T
13
to also be read from column Ca2. A final request packet at clock edge T
10
contains a PRE command.
The spacing between the request packets are constrained by the following timing parameters in the diagram:
t
RCD-R
, t
CC
, and t
RDP
. In addition, the spacing between the request and data packets is constrained by the t
CAC
parameter.
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2004-11-15
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TC59YM816BKG24A,32A,32B,40B,32C,40C
Table of Contents
Overview------------------------------------------------------------------------------------------------------------------------------- 1
Features-------------------------------------------------------------------------------------------------------------------------------- 1
XDR DRAM CSP
×16
Pin Out-------------------------------------------------------------------------------------------------- 1
Key Timing Parameters / Part Numbers------------------------------------------------------------------------------------- 1
Pin Assignment (top view) ------------------------------------------------------------------------------------------------------ 2
Key Timing Parameters/Part Numbers-------------------------------------------------------------------------------------- 2
Related Documentation----------------------------------------------------------------------------------------------------------- 2
General Description---------------------------------------------------------------------------------------------------------------- 3
Table of Contents------------------------------------------------------------------------------------------------------------------- 4
Lift of Tables-------------------------------------------------------------------------------------------------------------------------- 5
Lift of Figures------------------------------------------------------------------------------------------------------------------------- 6
Pin Description----------------------------------------------------------------------------------------------------------------------- 7
Block Diagram------------------------------------------------------------------------------------------------------------------------ 8
Request Packets------------------------------------------------------------------------------------------------------------------- 10
Request Packet Formats------------------------------------------------------------------------------------------------------- 10
Request Field Encoding-------------------------------------------------------------------------------------------------------- 12
Request Field Interactions----------------------------------------------------------------------------------------------------- 14
Request Interactions Cases--------------------------------------------------------------------------------------------------- 15
Dynamic Request Scheduling------------------------------------------------------------------------------------------------ 20
Memory Operations-------------------------------------------------------------------------------------------------------------- 22
Write Transactions--------------------------------------------------------------------------------------------------------------- 22
Read Transactions--------------------------------------------------------------------------------------------------------------- 24
Interleaved Transactions------------------------------------------------------------------------------------------------------- 26
Read/Write Interaction---------------------------------------------------------------------------------------------------------- 28
Propagation Delay---------------------------------------------------------------------------------------------------------- 30, 31
Register Operations-------------------------------------------------------------------------------------------------------------- 33
Serial Transactions-------------------------------------------------------------------------------------------------------------- 33
Serial Write Transaction-------------------------------------------------------------------------------------------------------- 33
Serial Read Transaction-------------------------------------------------------------------------------------------------------- 33
Register Summary--------------------------------------------------------------------------------------------------------------- 35
Maintenance Operations-------------------------------------------------------------------------------------------------------- 42
Refresh Transactions----------------------------------------------------------------------------------------------------------- 42
Interleaved Refresh Transactions-------------------------------------------------------------------------------------------- 42
Calibration Transactions-------------------------------------------------------------------------------------------------------- 44
Power State Management----------------------------------------------------------------------------------------------------- 45
Initialization------------------------------------------------------------------------------------------------------------------------ 47
XDR DRAM Initialization Overview------------------------------------------------------------------------------------------ 49
XDR DRAM Pattern Load with WDSL Register-------------------------------------------------------------------------- 50
Special Feature Description--------------------------------------------------------------------------------------------------- 52
Dynamic Width Control--------------------------------------------------------------------------------------------------------- 52
Write Masking--------------------------------------------------------------------------------------------------------------------- 54
Multiple Bank Sets and the ERAW Feature------------------------------------------------------------------------------- 56
Simultaneous Precharge------------------------------------------------------------------------------------------------------- 58
Operating Conditions------------------------------------------------------------------------------------------------------------ 59
Electrical Conditions------------------------------------------------------------------------------------------------------------- 59
Timing Conditions---------------------------------------------------------------------------------------------------------------- 60
Operating Characteristics------------------------------------------------------------------------------------------------------ 61
Electrical Characteristics------------------------------------------------------------------------------------------------------- 61
Supply Current Profile---------------------------------------------------------------------------------------------------------- 62
Timing Characteristics---------------------------------------------------------------------------------------------------------- 62
Timing Parameters-------------------------------------------------------------------------------------------------------------- 63
Receive/Transmit Timing------------------------------------------------------------------------------------------------------- 65
Clocking---------------------------------------------------------------------------------------------------------------------------- 65
RSL RQ Receive Timing------------------------------------------------------------------------------------------------------- 66
DRSL DQ Receive Timing----------------------------------------------------------------------------------------------------- 67
DRSL DQ Transmit Timing-----------------------------------------------------------------------------------------------------69
Serial Interface Receive Timing---------------------------------------------------------------------------------------------- 71
Serial Interface Transmit Timing--------------------------------------------------------------------------------------------- 72
Package Description------------------------------------------------------------------------------------------------------------- 73
Package Parasitic Summary-------------------------------------------------------------------------------------------------- 73
Package Mechanical Drawing------------------------------------------------------------------------------------------------ 75
Package Pin Numbering--------------------------------------------------------------------------------------------------------76
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2004-11-15
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TC59YM816BKG24A,32A,32B,40B,32C,40C
Table of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Pin Descriptions------------------------------------------------------------------------------------------------------ 7
Request Field Description---------------------------------------------------------------------------------------- 10
OP Field Encoding Summary------------------------------------------------------------------------------------ 12
ROP Field Encoding Summary----------------------------------------------------------------------------------12
POP Field Encoding Summary---------------------------------------------------------------------------------- 13
XOP Field Encoding Summary---------------------------------------------------------------------------------- 13
Packet Interaction Summary------------------------------------------------------------------------------------ 14
SCMD Field Encoding Summary------------------------------------------------------------------------------- 33
Initialization Timing Parameters-------------------------------------------------------------------------------- 48
WDSL-to-Core/DQ/SC Map (First Generation
×16/×8/×4
XDR DRAM, BL
=
16)---------------- 50
Core Data Word-to WDSL Format
------------------------------------------------------------------------ 51
Electrical Conditions--------------------------------------------------------------------------------------------- 59
Timing Conditions------------------------------------------------------------------------------------------------- 60
Electrical Characteristics--------------------------------------------------------------------------------------- 61
Supply Current Profile------------------------------------------------------------------------------------------- 62
Timing Characteristics------------------------------------------------------------------------------------------- 62
Timing Parameters-------------------------------------------------------------------------------------------- 63,64
Package RSL Parasitic Summary---------------------------------------------------------------------------- 73
CSP x16 Package Mechanical Parameters---------------------------------------------------------------- 75
Rev 0.85
2004-11-15
5/77
DSP and ARM Processors
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