EEWORLDEEWORLDEEWORLD

Part Number

Search

Q12.9990-32-50/100-3OT-TA-LF

Description
Parallel - Fundamental Quartz Crystal, 12.999MHz Nom, HC49/U, 2 PIN
CategoryPassive components    Crystal/resonator   
File Size3MB,2 Pages
ManufacturerJauch
Websitehttp://www.jauchusa.com/
Environmental Compliance
Download Datasheet Parametric View All

Q12.9990-32-50/100-3OT-TA-LF Overview

Parallel - Fundamental Quartz Crystal, 12.999MHz Nom, HC49/U, 2 PIN

Q12.9990-32-50/100-3OT-TA-LF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerJauch
package instructionHC49/U, 2 PIN
Reach Compliance Codecompli
Other featuresAT-CUT
Ageing5 PPM/ FIRST YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.01%
frequency tolerance50 ppm
load capacitance32 pF
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency12.999 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
physical size10.8 mm X 4.5 mm X 13 mm
Series resistance15 Ω
surface mountNO
Quartz Crystal · HC49/U
- Pin Type Crystal, 10.8 x 4.5 mm
- high frequency stability
- wave soldering temperature: 260 °C max.
- customized versions available, please ask
actual size
2011/65/EC
RoHS
RoHS compliant
Pb free
REACH
compliant
Conflict
mineral free
GENERAL DATA
TYPE
frequency range
S (HC49/U)
1.8432 ~ 40.0 MHz (fund. AT-cut)
20.0 ~ 105.0 MHz (3rd OT AT-cut)
50.0 ~ 175.0 MHz (5th OT AT-cut)
70.0 ~ 250.0 MHz (7th OT AT-cut)
frequency tolerance at 25 °C
load capacitance C
L
shunt capacitance C
O
storage temperature
drive level max.
aging
DIMENSIONS
13.0
±0.2
12.7 min.
4.5
±0.2
ESR (SERIES RESISTANCE RS)
frequency
in MHz
1.8432
2.0 ~ 2.999
3.0 ~ 3.499
3.57 ~ 6.999
7.00 ~ 12.999
13.0 ~ 40.000
20.0 ~ 29.999
30.0 ~ 105.00
50.0 ~ 175.00
70.0 ~ 250.00
vibration
mode
fund. - AT
fund. - AT
fund. - AT
fund. - AT
fund. - AT
fund. - AT
3rd OT - AT
3rd OT - AT
5th OT - AT
7th OT - AT
ESR max.
in ½
800
400
150
60
30
20
80
60
150
180
ESR typ.
in ½
400
150
50
20
15
10
35
30
60
80
±3 ppm ~ ±50 ppm
8 pF ~ 32 pF or series
< 7 pF
-55 °C ~ +125 °C
1.0 mW (100 µW recommended)
< ±5 ppm first year
TABLE 1: FREQUENCY STABILITY VS. TEMPERATURE
±3
ppm
±5
ppm
±10
ppm
±30
ppm
±50
ppm
±100
ppm
0 °C ~ +60 °C
-20 °C ~ +70 °C STD.
10.8
+0.25
10.0
±0.2
4.88
±0.2
-40 °C ~ +85 °C T1
-40 °C ~ +90 °C T4
-40 °C ~ +105 °C T2
-40 °C ~ +125 °C T3
standard
available
0.43
±0.03
in mm
MARKING
OPTION TABLE
frequency
company code / load capacitance
date code / internal code
TP
MP
TR
TA
= top pin
= middle pin
= tape and reel
= taped, ammo pack
KIS
IS
LL
PT
= spacer
= isolation spacer
= lead length in mm
= plastic tray
ORDER INFORMATION
Q
Quartz
frequency
1.8432 ~ 250.0 MHz
type
S
load capacitance
in pF
30 pF standard
12 pF ~ 32 pF
S for series
tolerance at
25 °C
±30 ppm std. > 1.8 MHz
±3 ppm ~±50 ppm on requ.
stability vs.
temp. range
> 3.5 MHz: stability see table,
on request
< 3.5 MHz: ±50 ppm
option
blank = -20 °C ~ +70 °C
T1 = -40 °C ~ +85 °C
T2 = -40 °C ~ +105 °C
T3 = -40 °C ~ +125 °C
T4 = -40 °C ~ +90 °C
FU = for fund. frequencies ≥ 20 MHz
3OT = 3rd overtone
5OT = 5th overtone
7OT = 7th overtone
other see option table
Example: Q 28.0-S-30-30/30-T1-FU-LF
(Suffix LF = RoHS compliant / Pb free pins)
25032019
info@jauch.com
Jauch Quartz GmbH • e-mail: info@jauch.de • full data can bedata can be found under:
full found under: www.jauch.com
All specifications are subject to change without notice
www.jauch.de | www.jauch.co.uk | www.jauch.fr | www.jauchusa.com
C6000TM Multicore DSP + Arm SoC Open Source
The DSP + Arm solution is optimized for embedded systems with a focus on power efficiency and real-time performance and includes OMAP-L1x and 66AK2x devices. OMAP-L1x devices are ideal for application...
Aguilera DSP and ARM Processors
【TI recommended course】#Lecture on basic knowledge of electronic circuits#
//training.eeworld.com.cn/TI/show/course/3818...
笑容在面 TI Technology Forum
Breakthrough TI BAW technology advances big data amidst the flood of information
[align=center][color=rgb(85, 85, 85)][font="][size=14px][color=rgb(204, 0, 0)][url=https://e2echina.ti.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-01-15/3302.asasas.jpg][i...
alan000345 TI Technology Forum
FPGA Learning Notes-----FPGA Competition Adventure
...
至芯科技FPGA大牛 FPGA/CPLD
Share: Component Failure Analysis Methods
[i=s]This post was last edited by qwqwqw2088 on 2021-10-29 12:57[/i]Once a device breaks down, don't stay away from it, but treat it as a treasure.Everyone who drives knows where is the best place to ...
qwqwqw2088 Power technology
7 good habits of PCB layout engineers
In the eyes of some people, the work of PCB layout engineers is a bit boring. Every day, they have to deal with thousands of wiring on the board, various packages, and repeat the work of pulling wires...
mwkjhl PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号