GS8162Z18(B/D)/GS8162Z36(B/D)
119, 165-bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- and 165-Bump BGA packages
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz 2.5
V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18(B/D)/36(B/D) may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162Z18(B/D)/36(B/D) is implemented with GSI's
high performance CMOS technology and is available in a
JEDEC-standard 119-bump and 165-bump BGA packages.
Functional Description
The GS8162Z18(B/D)/36(B/D) is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow Through
2-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
2.5
4.0
280
330
275
320
5.5
5.5
175
200
175
200
-225
2.7
4.4
255
300
250
295
6.0
6.0
165
190
165
190
-200
3.0
5.0
230
270
230
265
6.5
6.5
160
180
160
180
-166
3.4
6.0
200
230
195
225
7.0
7.0
150
170
150
170
-150
3.8
6.7
185
215
180
210
7.5
7.5
145
165
145
165
-133
4.0
7.5
165
190
165
185
8.5
8.5
135
150
135
150
Unit
ns
ns
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
Rev: 2.22 11/2005
1/35
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
京公网安备 11010802033920号
EEWORLD
