TDA7521 datasheet, PDF - EEWORLD Datasheet

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TDA7521: DescriptionAnalog Front End; CategoryAnalog mixed-signal IC The signal circuit; File Size93KB，11 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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TDA7521 Overview

Analog Front End

TDA7521 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Objectid	1484265530
Parts packaging code	QFP
package instruction	10 X 10 MM, 1.40 MM HEIGHT, TQFP-44
Contacts	44
Reach Compliance Code	compli
compound_id	4556148
Analog Integrated Circuits - Other Types	ANALOG CIRCUIT
JESD-30 code	S-PQFP-G44
JESD-609 code	e4
length	10 mm
Number of functions	1
Number of terminals	44
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BICMOS
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

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TDA7521

Analog Front End

PRODUCT PREVIEW

TDA7521 is a BiCMOS analog front end for CD appli-

cations. Four input signals (AC*, BD*, E* and F*),

coming from the pick-up (whose laser diode is driven

and controlled by the device itself), are preamplified

by a programmable voltage-to-voltage or current-to-

voltage stage, depending on the used pick-up. The

output signals from the preamplifier stage (AC, BD, E,

F and HF, a radio frequency signal obtained by com-

bining the photo-detector outputs as A+B+C+D) are

fed to an 8-bit HF ADC (for HF, which carries encoded

audio data) and a 6-bit Servo ADC (for AC, BD, E and

F, used for focusing, tracking the laser beam and con-

trolling revolution speed). All these signals are digi-

tized, multiplexed, synchronized with the external

clock (768×Fs or 394×Fs, Fs=44.1KHz) and fed to the

digital counterpart in one only digital stream (AC/HF/

BD/HF/E/HF/F/HF). Two stereo DACs convert the in-

put bitstreams from TDA7522.

TQFP44

(10 x 10 x 1.40 mm body)

All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All

TDA7521’s analog preprocessing is controlled by TDA7522 by means of an UART interface (which imple-

×10mm

package, TDA7521 features the functions

ments an I

C-like protocol). Housed in a TQFP 44, 10

shown in figure below.

TDA7521 uses the HF4CMOS technology and is supplied @5Vdc.

May 1998

This is preliminary information on a new product now in development. Details are subject to change without notice.

1/11

TDA7521

1.3 Laser driver section

The laser driver system is composed by the pick-up, the laser driver and the external PNP bipolar transis-

tor. It controls the external pick-up current level (up to 100mA) through its base current in order to maintain

a certain amount of diode power emission, independently from temperature and aging effects. This is done

in a digital way by using a 6-bit DAC to set the monitor diode analog reference voltage at a constant level

(and so the current in the laser diode). Thus, 26-1 different bias currents (with relative monitor voltage be-

tween 100 and 300mV) can be selected via UART interface. A negative feedback loop sets both the mon-

itor diode voltage and the laser diode bias current.

1.4 Preamplifier section

The goal of this section is to free the four voltage signals coming from either the CD pickup itself (voltage

inputs) or the internal current-to-voltage converters (current inputs) from their intrinsic DC component and

to amplify them to a level suitable for efficient A/D conversion. In case of current inputs, four transimped-

ance amplifiers convert the currents from AC (A+C), BD (B+D), E and F inputs into output voltages suitable

for the programmable preamplification chain; otherwise, this stage is by-passed and the voltage inputs are

directly connected to the preamplification stage. The two paths (for input current or input voltage) are dig-

itally selected via UART interface. In the same way also the gain of the path and the offset cancellation for

the preamplification chain are controlled (the gain programmability range is spanning from 6 up to 29.5dB

in 48 discrete steps of 0.5dB each, while the offset nulling circuit allows a minimum correction step of about

22mV via a 6-bit DAC). Moreover the preamplification chain generates an HF signal, which carries the en-

coded audio data and is obtained by combining the photo-detector outputs as A+B+C+D. All these signals

(AC, BD, E, F and HF), which can be evaluated by means of the monitor output, are fed to the ADC sec-

tion.

1.5 ADC section

The HF and servo (AC, BD, E and F) paths are digitized by means of two ADCs: the former (8-bit resolu-

tion, interleaved comparator two step architecture) samples the HF signal at a frequency of 384Fs (HFM)

or 192×Fs (LFM), the latter (6-bit resolution, interleaved comparator two step architecture) allows to mul-

tiplex the data for the servo path (AC, BD, E and F) in an only analog signal AC/BD/E/F and samples this

signal at 384×Fs (HFM) or 192×Fs (LFM); that means each servo signal is sampled at 96

×Fs

or 48×Fs).

Then both the bitstreams (HF and AC/BD/E/F) are digitally multiplexed in a single bitstream (AC/HF/BD/

HF/E/HF/F/HF). A SYNC signal (high during the period of HF before AC output) is provided in order to

point out the start of a new frame. It is worth noting that output data change on the falling edge of the mas-

ter clock.

The Table 1 shows the output data format for the ADC section: referring to AC/HF/BD/HF/E/ HF/F, the HF

signal have an

8-bit format which represents the digitized value of the HF analog signal

while the data for

the servo path (AC, BD, E and F) have a different format:6

bit for the digitized value of the analog output

from the preamplifiers plus underflow and overflow

(1)

Table 1. TDA7521 Output Format

LSB

D6/UF

MSB

D7/OF

Note: 1. Overflow and Underflow for the HF ADC are latched by a dedicated FSM and read via UART interface.

1.6 DAC section

In TDA7521 are present two 3rd order SC smoothing filters to be used in Digital-to-Analog conversion. Its

input signal is a bitstream created by a 2nd order digitalΣ∆ modulator present in TDA7522. From there

3/11

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