Data Sheet
FEATURES
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
AD9625
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
REFERENCE
VCM
VIN+
VIN–
RBIAS_EXT
CONTROL
REGISTERS
CMOS
DIGITAL
INPUT/
OUTPUT
LVDS
DIGITAL
INPUT/
OUTPUT
ADC
CORE
DDC
DIGITAL INTERFACE
AND CONTROL
12-bit 2.5 GSPS ADC, no missing codes
SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
Differential analog input: 1.2 V p-p
Differential clock input
3.2 GHz analog input bandwidth, full power
High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS
Subclass 1: 6.5 Gbps at 2.6 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
Supply voltages: 1.3 V, 2.5 V
Serial port control
Flexible digital output modes
Built-in selectable digital test patterns
Timestamp feature
Conversion error rate < 10
−15
f
S
/8 OR
f
S
/16
SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±
FD
RSTB
IRQ
SYNCINB±
DIVCLK±
SYSREF±
CLK±
CLOCK
MANAGEMENT
CMOS DIGITAL
INPUT/OUTPUT
AD9625
JESD204B
INTERFACE
SDIO
SCLK
CSB
Figure 1.
APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
GENERAL DESCRIPTION
The
AD9625
is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.6 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the
AD9625
is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and electronic countermeasures.
The analog input, clock, and SYSREF± signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C, measured at the case.
PRODUCT HIGHLIGHTS
1.
2.
3.
High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
Flexible digital data output formats based on the JESD204B
specification.
Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.
Rev. C
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AD9625* PRODUCT PAGE QUICK LINKS
Last Content Update: 03/25/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Informational
•
JESD204 Serial Interface
Press
•
2.6-GHz A/D Converter in High-Reliability Package Meets
Specific Sample Rate and Dynamic Range Requirements
of Aerospace/Defense Applications
•
Analog Devices Unveils 2.5-GSPS A/D Converter, Driver
Amplifier and Rapid Prototyping FMC Module
•
Global Leader in Converter Technology Releases
Industry’s Highest Performing 2-GSPS Data Converter
•
New PLLs Deliver Widest Frequency Range Coverage and
Lowest VCO Phase Noise in a Single Device
Technical Articles
•
A Test Method for Synchronizing Multiple GSPS
Converters
•
Designing High Speed Analog Signal Chains from DC to
Wideband
•
MS-2660: Understanding Spurious-Free Dynamic Range in
Wideband GSPS ADCs
•
MS-2670-1: The Demand for Digital: Challenges and
Solutions for High Speed Analog-to-Digital Converters
and Radar Systems
•
MS-2672: JESD204B Subclasses - Part 1: An Introduction to
JESD204B Subclasses and Deterministic Latency
•
MS-2677: JESD204B Subclasses - Part 2: Subclass 1 vs.
Subclass 2 System Considerations
•
MS-2702: Gigasample ADCs Run Fast to Solve New
Challenges
•
MS-2708: GSPS Data Converters to the Rescue for
Electronics Surveillance and Warfare Systems
•
MS-2714: Understanding Layers in the JESD204B
Specificaton: A High Speed ADC Perspective, Part 1
•
MS-2728: Demystifying the Conversion Error Rate of High
Speed ADCs
•
MS-2735: Maximizing the Dynamic Range of Software-
Defined Radio
•
Taming the Wideband Conundrum with RF Sampling
ADCs
EVALUATION KITS
• 2 AD9625 ADC’s running at 2.5GSPS with an effective
sampling rate of 5GSPS
•
AD9625 Evaluation and Synchronization
•
AD9625 Evaluation Board
•
ADA4961 & AD9625 Analog Signal Chain Evaluation and
Converter Synchronization
•
ADL5567 & AD9625 Analog Signal Chain Evaluation and
ADF4355-2 Wideband Synthesizer with VCO
DOCUMENTATION
Data Sheet
•
AD9625: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V
Analog-to-Digital Converter Data Sheet
User Guides
•
AD-FMCADC2-EBZ FMC Board User Guide
TOOLS AND SIMULATIONS
•
Visual Analog
•
AD9625 AMI Model
DESIGN RESOURCES
•
AD9625 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DISCUSSIONS
View all AD9625 EngineerZone Discussions.
DOCUMENT FEEDBACK
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AD9625
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 16
AD9625-2.0 ................................................................................. 17
AD9625-2.5 ................................................................................. 20
AD9625-2.6 ................................................................................. 24
Equivalent Test Circuits ................................................................. 27
Theory of Operation ...................................................................... 28
ADC Architecture ...................................................................... 28
Fast Detect ................................................................................... 28
Gain Threshold Operation ........................................................ 28
Test Modes ................................................................................... 29
Analog Input Considerations ........................................................ 30
Differential Input Configurations ............................................ 30
Using the ADA4961 ................................................................... 30
DC Coupling ............................................................................... 32
Clock Input Considerations ...................................................... 32
Digital Downconverters (DDC) ................................................... 33
Frequency Synthesizer and Mixer ............................................ 33
Data Sheet
Numerically Controlled Oscillator .......................................... 33
High Bandwidth Decimator ..................................................... 33
Low Bandwidth Decimator ....................................................... 36
Digital Outputs ............................................................................... 37
Introduction to the JESD204B Interface ................................. 37
Functional Overview ................................................................. 37
JESD204B Link Establishment ................................................. 39
Physical Layer Output................................................................ 43
Scrambler ..................................................................................... 43
Tail Bits ........................................................................................ 43
DDC Modes (Single and Dual) ................................................ 43
CheckSum ................................................................................... 44
8-Bit/10-Bit Encoder Control ................................................... 44
Initial Lane Alignment Sequence (ILAS) ................................ 44
Lane Synchronization ................................................................ 45
JESD204B Application Layers .................................................. 48
Frame Alignment Character Insertion .................................... 51
Thermal Considerations............................................................ 51
Power Supply Considerations ................................................... 51
Serial Port Interface (SPI) .............................................................. 52
Configuration Using the SPI ..................................................... 52
Hardware Interface..................................................................... 52
Memory Map .................................................................................. 53
Reading the Memory Map Register ......................................... 53
Memory Map Registers ............................................................. 53
Applications Information .............................................................. 71
Design Guidelines ...................................................................... 71
Power and Ground Recommendations ................................... 71
Clock Stability Considerations ................................................. 71
SPI Port ........................................................................................ 71
Outline Dimensions ....................................................................... 72
Ordering Guide .......................................................................... 72
Rev. C | Page 2 of 72
Data Sheet
REVISION HISTORY
9/2016—Rev. B to Rev. C
Changes to ADC Output Control Bits on JESD204B Samples
Section ..............................................................................................45
Changes to Table 94 ........................................................................67
Changes to Table 110 and Table 111 .............................................69
Changes to Table 113 and Table 114 .............................................70
Changes to the Clock Stability Considerations Section .............71
Changes to Ordering Guide ...........................................................72
5/2015—Rev. A to Rev. B
Added AD9625-2.6 ....................................................... Throughout
Change to Figure 1 ............................................................................ 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Change to Figure 5 ..........................................................................10
Added Endnote 1, Table 8 ..............................................................11
Added Endnote 2, Table 9 ..............................................................13
Added AD9625-2.6 Section ...........................................................24
Changes to Figure 61 and Figure 63 .............................................27
Changes to Table 11 ........................................................................30
Added Using the ADA4961 Section .............................................30
Added Figure 77; Renumbered Sequentially, Figure 78,
Figure 79, and Figure 80 .................................................................31
Changes to Table 12 ........................................................................34
Changes to Low Bandwidth Decimator Section and Table 13.....36
Changes to Table 28 ........................................................................54
Changes to Table 107 ......................................................................69
Changes to Ordering Guide ...........................................................72
9/2014—Rev. 0 to Rev. A
Added AD9625-2.5 ....................................................... Throughout
Changes to Features and General Description Sections .............. 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Figure 3 and Figure 4.................................................... 8
Changes to Table 6 ............................................................................ 9
Changes to Pin K4; Figure 5, Table 8, and Table 9 ......................10
Added Typical Performance Characteristics Summary and
Changes to Typical Performance Characteristics .......................16
AD9625
Changes to Figure 45, Figure 49, and Figure 50; Added
Figure 51 to Figure 54 ..................................................................... 23
Changes to Gain Threshold Operation Section .......................... 24
Changes to Analog Input Considerations Section...................... 26
Changes to Digital Downconverters (DDC) Section ................. 28
Added Figure 68 .............................................................................. 32
Changes to Data Streaming Section; Added Link Setup
Parameters Section.......................................................................... 33
Changes to Digital Outputs, Timing, and Controls Section and
Table 15 ............................................................................................. 34
Changes to Table 16 and Table 17 ................................................. 35
Added Table 18 ................................................................................ 36
Added Multichip Synchronization Using SYSREF± Timestamp,
Six Lane Output Mode, and SYSREF± Setup and Hold IRQ
Sections ............................................................................................. 39
Added IRQ Guardband Delays (SYSREF± Setup and Hold)
Section .............................................................................................. 40
Added Using Rising/Falling Edges of CLK to Latch SYSREF±
Section .............................................................................................. 41
Changes to Configuration Using the SPI Section ....................... 46
Changes to Transfer Register Map Section, Table 26, and
Table 27 ............................................................................................. 47
Changes to Table 28, Table 29, and Table 30 ............................... 48
Changes to Table 33 and Table 34 ................................................. 49
Changes to Table 53 ........................................................................ 52
Changes to Table 54 ........................................................................ 52
Changes to Table 58 ........................................................................ 54
Changes to Table 71 ........................................................................ 56
Changes to Table 79 and Table 80 ................................................. 57
Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and
Table 86 ............................................................................................. 58
Changes to Table 89 ........................................................................ 59
Changes to Table 92 and Table 93 ................................................. 60
Changes to Table 94, Table 97, and Table 98 ............................... 61
Changes to Table 101 and Table 106 ............................................. 62
Added Table 107 and Table 108..................................................... 63
Added Table 115 and Table 116..................................................... 64
Added Applications Information Section .................................... 65
Changes to Ordering Guide ........................................................... 66
5/2014—Revision 0: Initial Version
Rev. C | Page 3 of 72
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