A1280A-PGG176B datasheet, PDF - EEWORLD Datasheet

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A1280A-PGG176B: DescriptionField Programmable Gate Array, 1232 CLBs, 8000 Gates, 41MHz, CMOS, CPGA176, CERAMIC, PGA-176; CategoryProgrammable logic devices Programmable logic; File Size653KB，38 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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A1280A-PGG176B Overview

Field Programmable Gate Array, 1232 CLBs, 8000 Gates, 41MHz, CMOS, CPGA176, CERAMIC, PGA-176

A1280A-PGG176B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	CERAMIC, PGA-176
Reach Compliance Code	compli
Other features	MAX 140 I/OS
maximum clock frequency	41 MHz
Combined latency of CLB-Max	5 ns
JESD-30 code	S-CPGA-P176
JESD-609 code	e4
length	39.878 mm
Configurable number of logic blocks	1232
Equivalent number of gates	8000
Number of terminals	176
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1232 CLBS, 8000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	4.3688 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	39.878 mm

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v4.0.1

ACT

™

2 Family FPGAs

Fe a t ur es

• Up to 8000 Gate Array Gates

(20,000 PLD equivalent gates)

• Replaces up to 200 TTL Packages

• Replaces up to eighty 20-Pin PAL

Packages

• Datapath Performance at 105 MHz

• 16-Bit Accumulator Performance to 39 MHz

• Two In-Circuit Diagnostic Probe Pins Support Speed

Analysis to 50 MHz

• Two High-Speed, Low-Skew Clock Networks

• I/O Drive to 10 mA

• Nonvolatile, User Programmable

• Logic Fully Tested Prior to Shipment

• 1.0-micron CMOS Technology

• Design Library with over 500 Macro Functions

• Single-Module Sequential Functions

• Wide-Input Combinatorial Functions

• Up to 1232 Programmable Logic Modules

• Up to 998 Flip-Flops

Pr od uc t F am i l y P r o f i l e

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

Logic Modules

S-Modules

C-Modules

Flip-Flops (maximum)

Routing Resources

Horizontal Tracks/Channel

Vertical Tracks/Channel

PLICE Antifuse Elements

User I/Os (maximum)

Packages

A1225A

2,500

6,250

451

231

220

382

250,000

100 CPGA

100 PQFP

100 VQFP

84 PLCC

A1240A

4,000

10,000

100

684

348

336

568

400,000

104

132 CPGA

144 PQFP

176 TQFP

84 PLCC

A1280A

8,000

20,000

200

1,232

624

608

998

750,000

140

176 CPGA

160 PQFP

176 TQFP

84 PLCC

172 CQFP

85 MHz

67 MHz

36 MHz

Performance

16-Bit Prescaled Counters

16-Bit Loadable Counters

16-Bit Accumulators

105 MHz

70 MHz

39 MHz

100 MHz

69 MHz

38 MHz

Notes:

1. See the

“Product Plan” on page 3

for package availability.

2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,

dated 3-28-93, any analysis is not endorsed by PREP.

D e ce m b e r 2 0 0 0

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