5962-0151503QXX datasheet, PDF

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5962-0151503QXX: DescriptionField Programmable Gate Array, 72000 Gates, CMOS, CQFP256, CERAMIC, QFP-256; CategoryProgrammable logic devices Programmable logic; File Size171KB，21 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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5962-0151503QXX Overview

Field Programmable Gate Array, 72000 Gates, CMOS, CQFP256, CERAMIC, QFP-256

5962-0151503QXX Parametric

Parameter Name	Attribute value
Maker	Actel
package instruction	CERAMIC, QFP-256
Reach Compliance Code	unknow
Other features	IT CAN ALSO OPERATES 5V SUPPLY ALSO
JESD-30 code	S-CQFP-F256
length	36 mm
Equivalent number of gates	72000
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	72000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.9 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	QUAD
width	36 mm

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REVISIONS

LTR

DESCRIPTION

Changes made to Table 1, updated paragraph 4.4.1f, and editorial

changes throughout. ksr

Constant acceleration changed for class Q and V to condition B for

case outline Y and remains condition D for devices built with case

outline X. ksr

Added T

and T

to section 1.4, and updated boilerplate paragraphs.

ksr

Added devices 05 – 08; Update to 1.3, made changes to IIL and IOZ

in Table I, made change to paragraph 4.2.2 and 4.4.1f, and updated

boilerplate paragraphs. ksr

Editorial changes to paragraphs 4.3 and 4.4. ksr

DATE (YR-MO-DA)

03-02-21

03-09-08

APPROVED

Raymond Monnin

04-01-04

04-08-27

Raymond Monnin

05-09-29

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Kenneth Rice

CHECKED BY

Raj Pithadia

APPROVED BY

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

Raymond Monnin

DRAWING APPROVAL DATE

02 - 02 - 25

REVISION LEVEL

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

MICROCIRCUIT, MEMORY, DIGITAL,

CMOS, FIELD PROGRAMMABLE GATE

ARRAY, 72,000 GATES, MONOLITHIC

SILICON

SIZE

CAGE CODE

SHEET

67268

5962-01515

5962-E514-05

DSCC FORM 2233

APR 97

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DoDISS

cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DoDISS are the issues of the

documents cited in the solicitation.

AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)

ASTM Standard F1192M-95 -

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials,

1916 Race Street, Philadelphia, PA 19103.)

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington,

VA 22201.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the

documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless

a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s).

3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered

item drawing is not part of this drawing. When required in screening (see 4.2 herein) or qualification conformance inspection,

groups A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 90

percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for

any altered item drawing pattern.

3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached

altered item drawing.

3.2.4 Switching test circuit and waveforms. The switching test circuit and waveforms diagram shall be as specified on

figure 3.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-01515

SHEET

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 42 (see MIL-PRF-38535, appendix A).

3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in

a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing.

3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1

and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program

configuration.

3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions

herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery.

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

Interim and final electrical test parameters shall be as specified in table IIA herein.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-01515

SHEET

5962-0151503QXX Related Products

	5962-0151503QXX	5962-0151502QXX	5962-0151501QYX	5962-0151502QYX	5962-0151503QYX	5962-0151504QXX	5962-0151504QYX
Description	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP208, CERAMIC, QFP-208	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP208, CERAMIC, QFP-208	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP208, CERAMIC, QFP-208	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP256, CERAMIC, QFP-256	Field Programmable Gate Array, 72000 Gates, CMOS, CQFP208, CERAMIC, QFP-208
Maker	Actel	Actel	Actel	Actel	Actel	Actel	Actel
package instruction	CERAMIC, QFP-256	CERAMIC, QFP-256	CERAMIC, QFP-208	CERAMIC, QFP-208	CERAMIC, QFP-208	CERAMIC, QFP-256	CERAMIC, QFP-208
Reach Compliance Code	unknow	unknown	unknow	unknow	unknow	unknow	unknow
Other features	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO	IT CAN ALSO OPERATES 5V SUPPLY ALSO
JESD-30 code	S-CQFP-F256	S-CQFP-F256	S-CQFP-F208	S-CQFP-F208	S-CQFP-F208	S-CQFP-F256	S-CQFP-F208
length	36 mm	36 mm	29.21 mm	29.21 mm	29.21 mm	36 mm	29.21 mm
Equivalent number of gates	72000	72000	72000	72000	72000	72000	72000
Number of terminals	256	256	208	208	208	256	208
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	72000 GATES	72000 GATES	72000 GATES	72000 GATES	72000 GATES	72000 GATES	72000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF	QFF	QFF	QFF	QFF	QFF	QFF
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q
Maximum seat height	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	36 mm	36 mm	29.21 mm	29.21 mm	29.21 mm	36 mm	29.21 mm

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