ASM705 / 706 / 707 / 708
ASM813L
February 2005
rev 1.5
Low Power µP Supervisor Circuits
General Description
The ASM705 / 706 / 707 / 708 and AS813L are cost effective
CMOS supervisor circuits that monitors power-supply and
battery voltage level, and µP/µC operation.
The family offers several functional options. Each device
generates a reset signal during power-up, power-down and
during brownout conditions. A reset is generated when the
supply drops below 4.65V (ASM705/707/813L) or 4.40V
(ASM706/708). For 3V power supply applications, refer to the
ASM705P/R/S/T data sheet. In addition, the ASM705/706/813L
feature a 1.6 second watchdog timer. The ASM707/708 have
both active-HIGH and active-LOW reset outputs but no
watchdog function. The ASM813L has the same pin-out and
functions as the ASM705 but has an active-HIGH reset output.
A versatile power-fail circuit has a 1.25V threshold, useful in low
battery detection and for monitoring non-5V supplies. All
devices have a manual reset (MR) input. The watchdog timer
output will trigger a reset if connected to MR.
All devices are available in 8-pin DIP, SO and MicroSO
packages.
•
•
•
•
•
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Features
•
Precision power supply monitor
•4.65V threshold (ASM705/707/813L)
•4.40V threshold (ASM706/708)
Debounced manual reset input
Voltage monitor
•1.25V threshold
•Battery monitor / Auxiliary supply monitor
Watchdog timer (ASM705/706/813L)
200ms reset pulse width
Active HIGH reset output (ASM707/708/813L)
MicroSO package
Applications
•
•
•
•
•
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Computers and embedded controllers
Portable/Battery-operated systems
Intelligent instruments
Wireless communication systems
PDAs and hend-held equipment
Automative Systems
Safety Systems
Typical Operating Circuit
Unregulated DC
+5V Regulator
R
1
V
CC
PFI
RESET
(RESET)
V
CC
µP
RESET
(RESET)
I/O LINE
NMI
INTERRUPT
R
2
ASM705
WDI
ASM706
(ASM813L)
WDO
PFO
MR
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
February 2005
rev 1.5
ASM705 / 706 / 707 / 708
ASM813L
Block Diagrams
WDI
Transition
Detector
V
CC
0.25mA
Watchdog
Timer
Timebase
RESET
Generator
WDO
V
CC
0.25mA
RESET
MR
RESET
(RESET) ASM813L
MR
RESET
Generator
RESET
V
CC
+
+
-
V
CC
+
+
-
4.65V (ASM705/813L)
4.40V (ASM706)
+
4.65V (ASM707)
4.40V (ASM708)
+
PFI
PFI
PFO
1.25V
ASM705
ASM706
ASM813L
1.25V
-
-
PFO
ASM707
ASM708
GND
GND
Pin Configuration
DIP/SO
MR
V
CC
1
2
ASM707
ASM708
8 RESET
7 RESET
6
5
NC
PFO
8 WDO
ASM705
V
CC
2
7 RESET (RESET)
ASM706
GND 3
(ASM813L)
6 WDI
5 PFO
PFI 4
MR
1
RESET
1
ASM707
ASM708
8
7
6
5
NC
RESET 2
MR 3
V
CC
4
MicroSO
RESET (RESET)
WDO
1
2
ASM705
8
WDI
PFO
PFI
GND
PFO
PFI
GND
7
ASM706
MR 3
(ASM813L)
6
V
CC
4
5
GND 3
PFI
4
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
2 of 16
February 2005
rev 1.5
ASM705 / 706 / 707 / 708
ASM813L
Pin Description
Pin Number
ASM705/706
DIP/
SO
MicroSO
ASM707/708
DIP/
SO
MicroSO
ASM813L
DIP/
SO
MicroSO
Manual reset input. The active LOW input triggers a reset
pulse. A 250 µA pull-up current allows the pin to be
driven by TTL/CMOS logic or shorted to ground with a
switch.
+5V power supply input.
Ground reference for all signals.
Power-fail input voltage monitor. With PFI less than
1.25V, PFO goes LOW. Connect PFI to Ground or V
CC
when not in use.
Power-fail output. The output is active LOW and sinks
current when PFI is less than 1.25V.
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6sec at WDI allows
the internal timer to run-out, setting WDO LOW. The
watchdog function is disabled by floating WDI or by con-
necting WDI to a high impedance three-state buffer. The
internal watchdog timer clears when: RESET is asserted;
WDI is three-stated ; or WDI sees a rising or falling edge.
Not Connected
Active LOW reset output. Pulses LOW for 200ms when
triggered, and stays LOW whenever V
CC
is below the
reset threshold. RESET remains LOW for 200ms after
V
CC
rises above the reset threshold or MR goes from
LOW to HIGH. A watchdog timeout will not trigger
RESET unless WDO is connected to MR.
Watchdog output. WDO goes LOW when the 1.6 second
internal watchdog timer times-out and does not go HIGH
until the watchdog is cleared. In addition, when V
CC
falls
below the reset threshold, WDO goes LOW. Unlike
RESET, WDO does not have a minimum pulse width and
as soon as V
CC
exceeds the reset threshold, WDO goes
HIGH with no delay.
Active HIGH reset output. The inverse of RESET. The
ASM813L only has a RESET output.
Name
Function
1
3
1
3
1
3
MR
2
3
4
5
2
3
4
5
2
3
4
5
V
CC
GND
4
6
4
6
4
6
PFI
5
7
5
7
5
7
PFO
6
8
-
-
6
8
WDI
-
-
6
8
-
-
NC
7
1
7
1
-
-
RESET
8
2
-
-
8
2
WDO
-
-
8
2
7
1
RESET
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
3 of 16
February 2005
rev 1.5
ASM705 / 706 / 707 / 708
ASM813L
Detailed Description
A
proper
reset
input
enables
a
microprocessor
/
V
CC
V
RT
5V
0V
5V
RESET
microcontroller to start in a known state. ASM70X and
ASM813L assert reset to prevent code execution errors
during power-up, power-down and brown-out conditions.
RESET/RESET Timing
The RESET/RESET signals are designed to start a µP/µC in
a known state or return the system to a known state.
The ASM707/708 have two reset outputs, one active-HIGH
RESET and one active-LOW RESET output. The ASM813L
has only an active-HIGH output. RESET is simply the
complement of RESET.
t
RS
t
RS
0V
5V
MR
0V
5V
WDO
MR externally
set low
t
MD
t
MR
0V
Figure 1: WDI Three-state operation
RESET is guaranteed to be LOW with V
CC
above 1.2V.
During a power-up sequence, RESET remains low until the
supply rises above the threshold level, either 4.65V or 4.40V.
RESET goes high approximately 200ms after crossing the
threshold.
During power-down, RESET goes LOW as V
CC
falls below
the threshold level and is guaranteed to be under 0.4V with
V
CC
above 1.2V.
In a brownout situation where V
CC
falls below the threshold
level, RESET pulses low. If a brown-out occurs during an
already initiated reset, the pulse will continue for a minimum
of 140ms.
Power Failure Detection With Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor
with an external resistor voltage divider. The attenuated
voltage at PFI should be set just below the 1.25 threshold. As
the supply level falls, PFI is reduced causing the PFO output
to transit LOW. Normally PFO interrupts the processor so the
system can be shut down in a controlled manner.
If WDI is floated or connected to a three-stated circuit, the
watchdog function is disabled, meaning, it is cleared and not
counting. The watchdog timer is also disabled if RESET is
asserted. When RESET becomes inactive and the WDI input
sees a high or low transition as short as 50ns, the watchdog
timer will begin a 1.6 second countdown. Additional
Watchdog Timer
The watchdog timer available on the ASM705/706/813L
monitors µP/µC activity. An output line on the processor is
used to toggle the WDI line. If this line is not toggled within
1.6 seconds, the internal timer puts the watchdog output,
WDO, into a LOW state. WDO will remain LOW until a toggle
is detected at WDI.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250µA
pull-up current and can be driven low by CMOS/TTL logic or
a mechanical switch to ground. An external debounce circuit
is unnecessary since the 140ms minimum reset time will
debounce mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a
watchdog timeout forces RESET to be generated. The
ASM813L should be used when an active-HIGH RESET is
required.
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
4 of 16
February 2005
rev 1.5
transitions at WDI will reset the watchdog timer and initiate a
new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, V
CC
, falls below the device threshold level.
WDO goes HIGH as soon as V
CC
transitions above the
threshold. There is no minimum pulse width for WDO as
there is for the RESET outputs. If WDI is floated, WDO
essentially acts as a low-power output indicator.
Supply Voltage
ASM705 / 706 / 707 / 708
ASM813L
BUF
Buffered
RESET
V
CC
ASM70x
4.7kΩ
RESET
GND
µC or µP
RESET
Input
GND
WDI
Bi-directional I/O Pin
Figure 3: Bi-directional Reset Pin Interfacing
WDO
Monitoring Voltages Other Than V
CC
The ASM705-708 can monitor voltages other than V
CC
using
the Power Fail circuitry. If a resistive divider is connected
RESET
from the voltage to be monitored to the Power Fail input
(PFI), the PFO will go LOW if the voltage at PFI goes below
1.25V reference. Should hysteresis be desired, connect a
resistor (equal to approximately 10 times the sum of the two
RESET
resistors in the divider) between the PFI and PFO pins. A
capacitor between PFI and GND will reduce circuit sensitivity
to input high-frequency noise. If it is desired to assert a
Figure 2: Watchdog Timing
RESET for voltages other than V
CC
then the PFO output is to
be connected to the MR.
Application Information
V
IN
Ensuring That RESET is Valid Down to V
CC
= 0V
When V
CC
falls below 1.1V, the ASM705-708 RESET output
no longer pulls down; it becomes indeterminate. To avoid the
possibility that stray charges build up and force RESET to the
wrong state, a pull-down resistor should be connected to the
RESET pin, thus draining such charges to ground and
holding RESET low. The resistor value is not critical. A 100kΩ
resistor will pull RESET to ground without loading it.
Bi-directional Reset Pin Interfacing
The ASM705/6/7/8 can interface with µP/µC bi-directional
reset pins by connecting a 4.7kΩ resistor in series with the
RESET output and the µP/µC bi-directional RESET pin.
R
2
R
1
+5V
V
CC
MR
ASM70x
PFI
PFO
GND
RESET
To
µP
Figure 4: Monitoring +5V and an additional supply V
IN
5 of 16
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
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