EP9604-650 datasheet, PDF - EEWORLD Datasheet

EP9604-650: Description5 Tap High Speed CMOS (HCT) Compatible Active Delay Lines; Categorylogic logic; File Size17KB，1 Pages; ManufacturerPCA Electronics Inc.; Websitehttp://www.pca.com/

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EP9604-650 Overview

5 Tap High Speed CMOS (HCT) Compatible Active Delay Lines

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	PCA Electronics Inc.
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14/8
Reach Compliance Code	compli
Other features	MAX RISE TIME CAPTURED
series	9604
Input frequency maximum value (fmax)	1.53846 MHz
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
Logic integrated circuit type	ACTIVE DELAY LINE
Humidity sensitivity level	3
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Maximum supply current (ICC)	15 mA
programmable delay line	NO
Prop。Delay @ Nom-Su	650 ns
Certification status	Not Qualified
Maximum seat height	6.35 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Total delay nominal (td)	650 ns
width	7.62 mm

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