DDRI UNBUFFERED VLP DIMM
VR4VUxxxx28xBx
Features
•
Single Power Supply: 2.5V
±
0.2V (266MHz, 333MHz) or 2.6V
±
0.1V (400MHz)
•
•
•
•
•
•
•
•
•
Double Data Rate architecture; two data transfers per clock cycle.
Source-synchronous data strobes.
Differential clock inputs (CLK, #CLK).
MRS cycle with address key programs.
Read CAS latency
Burst Length (2, 4, and 8)
Burst type (Sequential & Interleave)
All inputs except Data & DM are sampled at the positive edge of the system clock.
Auto & Self-Refresh.
4k/15.625us (128Mbit) and 8k/8.125us (256Mb, 512Mb) average Refresh Period.
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS4VUxxxx28xBx Revision A Created By: Brian Ouellette
Page 2 of 17
DDRI UNBUFFERED VLP DIMM
VR4VUxxxx28xBx
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VREF
DQ0
GND
DQ1
DQS0
DQ2
VDD
DQ3
NC
*#RST
GND
DQ8
DQ9
DQS1
VDDQ
CLK1
#CLK1
GND
DQ10
DQ11
CKE0
VDDQ
DQ16
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
GND
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
GND
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
GND
A1
†
CB0
†
CB1
VDD
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
†
CB2
GND
†
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
GND
BA0
DQ35
DQ40
VDDQ
#WE
DQ41
#CAS
GND
DQS5
DQ42
DQ43
Pin
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDD
*#CS2
DQ48
DQ49
GND
#CLK2
CLK2
VDDQ
DQS6
DQ50
DQ51
GND
*VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
GND
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
GND
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
GND
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
**
CKE1
VDDQ
*
BA2
DQ20
§
A12
Pin
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
GND
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
GND
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
GND
DQ31
†
CB4
†
CB5
VDDQ
CLK0
#CLK0
Pin
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
GND
DM8
A10
†
CB6
VDDQ
†
CB7
GND
DQ36
DQ37
VDD
DM4
DQ38
DQ39
GND
DQ44
#RAS
DQ45
VDDQ
#CS0
**
#CS1
DM5
GND
DQ46
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
*
#CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
GND
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
* Pins are not used in this module
** Pins are not connected or used on single rank modules
† Pins are not used for x64 modules
§
Pin is not used on modules based on 128Mbit devices (Cxx at end of PN).
ADDRESSING
DDR Device
Row address
Column address
Device banks
Refresh Count
128Mbit
(CBx suffix)
A0 ~ A11
A0 ~ A9
BA0 ~ BA1 (4)
4k
256Mbit
(DBx suffix)
A0 ~ A12
A0 ~ A9
BA0 ~ BA1 (4)
8k
512Mbit
(EBx suffix)
A0 ~ A12
A0 ~ A9, A11
BA0 ~ BA1 (4)
8k
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS4VUxxxx28xBx Revision A Created By: Brian Ouellette
Page 3 of 17
DDRI UNBUFFERED VLP DIMM
VR4VUxxxx28xBx
PIN FUNCTION DESCRIPTION
SIGNAL
A0 ~ An
FUNCTION
DIRECTION
DESCRIPTION
Provides row / column addresses on the rising edge of CLK.
During a PRECHARGE command, a VIH level on A10 precharges all
device banks and a VIL level precharges one bank selected by
BA0~BAn. During a MRS command, address lines provide the op
code.
Selects device bank that a command is applied to.
Differential module clock used to sample address, control, and data
lines. The timing reference point for address and control is the
positive edge of CLK; output data and DQS are defined by CLK and
#CLK crossing.
Disables (low) or activates (high) internal device clocks, inputs, and
buffers. Provides power savings during Precharge Power-Down,
Self-Refresh, and Active Power-Down operations. CKE enters and
exits all modes synchronously except for output buffer disable and
Self-Refresh exit which are asynchronous. CKE must be kept high for
Read and Write operations.
Command bit used to enable (low) or mask (high) incoming
commands on the positive clock edge.
Define the command being entered on the positive clock edge.
Data inputs / outputs.
ECC check bits.
Source-synchronous signal, edge-aligned output with read data and
center-aligned input with write data.
Masks write data if high. Sampled on both the rising and falling
edges of the DQS.
Asynchronously sets register outputs low during initialization.
Transfers serial address and data to/from the SPD EEPROM. Open
drain, requires external pullup to VDDSPD.
Clock signal for the SPD EEPROM. Requires external pullup to
VDDSPD.
Tied to either GND or VDDSPD on the motherboard to configure the
SPD EEPROM address range.
SDRAM reference I/O power supply.
Power supply voltage for data and DQS buffers.
SPD EEPROM power, 2.2 to 5.5V.
A no connect / open indicates that VDD = VDDQ.
Module power / ground supply
No Connection
Address
Input
BA0 ~ BAn
CLK0 ~ CLK2,
#CLK0 ~ #CLK2
Bank Select Address
Master Clock
Input
Input
CKE0, CKE1
Clock Enable
Input
#CS0, #CS1
#CAS, #RAS,
#WE
DQ0 ~ DQ63
CB0 ~ CB7
DQS0 ~ DQS8
DM0 ~ DM8
#RST
SDA
SCL
SA0 ~ SA2
VREF
VDDQ
VDDSPD
VDDID
VDD/GND
NC
Chip Select
Command bits
Data input/output
Check Bit
Data Strobe
Data Mask
Reset
EEPROM Data
EEPROM Clock
EEPROM Select
Reference Supply
I/O Supply Voltage
SPD power
VDD Identification Flag
Power Supply/ Ground
N/A
Input
Input
Bi-directional
Bi-directional
Bi-directional
Input
Input
Bi-directional
Input
Input
Power Input
Power Input
Power Input
Output
Power Input
N/A
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS4VUxxxx28xBx Revision A Created By: Brian Ouellette
Page 4 of 17
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
