EN25S40-75XIP datasheet, PDF - EEWORLD Datasheet

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EN25S40-75XIP: Description4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector; File Size587KB，37 Pages; ManufacturerEon; Websitehttp://www.essi.com.tw/

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EN25S40-75XIP Overview

4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

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EN25S40

4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

FEATURES

•

Single power supply operation

- Full voltage range: 1.65-1.95 volt

•

Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

•

4 M-bit Serial Flash

- 4 M-bit/512 K-byte/2048 pages

- 256 bytes per programmable page

•

Standard or Dual SPI

- Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#

- Dual SPI: CLK, CS#, DQ

, DQ

, WP#, HOLD#

•

High performance

- 75MHz clock rate for one data bit

- 50MHz clock rate for two data bits

•

Low power consumption

- 7 mA typical active current

- 1

μA

typical power down current

•

Uniform Sector Architecture:

128 sector of 4-Kbyte

8 blocks of 64-Kbyte

Any sector or block can be erased individually

•

Software and Hardware Write Protection:

- Block Protect Bits are default set to “1” at

Power-up

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

•

High performance program/erase speed

Page program time: 1.3ms typical

Sector erase time: 90ms typical

Block erase time 400ms typical

Chip erase time: 3.5 seconds typical

•

Lockable 256 byte OTP security sector

•

Minimum 100K endurance cycle

•

Package Options

8 pins SOP 150mil body width

8 contact VDFN 2x3mm

8 contact VDFN 5x6 mm

All Pb-free packages are RoHS compliant

•

Industrial temperature Range

GENERAL DESCRIPTION

The EN25S40 is a 4 Megabit (512K-byte) Serial Flash memory, with advanced write protection

mechanisms. The EN25S40 supports the standard Serial Peripheral Interface (SPI), and a high

performance Dual output as well as Dual I/O using SPI pins: Serial Clock, Chip Select, Serial DQ

(DI),

(DO), WP# and HOLD#. SPI clock frequencies of up to 50MHz are supported allowing equivalent

clock rates of 100MHz for Dual Output when using the Dual Output Fast Read instructions. The

memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The EN25S40 is designed to allow either single

Sector/Block

at a time or full chip erase operation. The

EN25S40 can be configured to protect part of the memory as the software protected mode. The device

can sustain a minimum of 100K program/erase cycles on each sector

or block

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

Rev. A, Issue Date: 2009/04/28

EN25S40

SIGNAL DESCRIPTION

Serial Data Input, Output and IOs (DI, DO and DQ

, DQ

)

The EN25S40 support standard SPI and Dual SPI operation. Standard SPI instructions use the

unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising

edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read

data or status from the device on the falling edge CLK.

Dual SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the

device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is

deselected and the Serial Data Output (DO, or DQ

and DQ

) pins are at high impedance. When

deselected, the devices power consumption will be at standby levels unless an internal erase, program

or status register cycle is in progress. When CS# is brought low the device will be selected, power

consumption will increase to active levels and instructions can be written to and data read from the

device. After power-up, CS# must transition from high to low before a new instruction will be accepted.

HOLD (HOLD#)

The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought

low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be

ignored (don’t care). The HOLD# function can be useful when multiple devices are sharing the same

SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

Rev. A, Issue Date: 2009/04/28

EN25S40-75XIP Related Products

	EN25S40-75XIP	EN25S40-75GI	EN25S40-75WI	EN25S40-75XI
Description	4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector	4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector	4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector	4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

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