April 2005
®
AS7C33512NTD32A
AS7C33512NTD36A
3.3V 512K × 32/36 Pipelined SRAM with NTD
TM
Features
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 32 or 36 bits
NTD
™
architecture for efficient bus operation
Fast clock speeds to 166 MHz
Fast clock to data access: 3.4/3.8 ns
Fast OE access time: 3.4/3.8 ns
Fully synchronous operation
Asynchronous output enable control
Available in 100-pin TQFP packages
Individual byte write and global write
•
•
•
•
•
•
•
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[18:0]
19
D
Address
register
Burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
512K x 32/36
SRAM
Array
DQ[a,b,c,d]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.4
300
90
60
-133
7.5
133
3.8
275
80
60
Units
ns
MHz
ns
mA
mA
mA
4/21/05, v 2.8
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512NTD32A/36A
®
16 Mb Synchronous SRAM products list
1,2
Org
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
Part Number
AS7C331MPFS18A
AS7C33512PFS32A
AS7C33512PFS36A
AS7C331MPFD18A
AS7C33512PFD32A
AS7C33512PFD36A
AS7C331MFT18A
AS7C33512FT32A
AS7C33512FT36A
AS7C331MNTD18A
AS7C33512NTD32A
AS7C33512NTD36A
AS7C331MNTF18A
AS7C33512NTF32A
AS7C33512NTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
3
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
4/21/05, v 2.8
Alliance Semiconductor
P. 2 of 18
AS7C33512NTD32A/36A
®
100-pin TQFP - top view
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
NC/DQPc
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
NC
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
NC/DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
92
91
90
89
88
87
86
85
84
83
82
81
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
SS
NC
V
DD
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQPa/NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
4/21/05, v 2.8
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Alliance Semiconductor
P. 3 of 18
AS7C33512NTD32A/36A
®
Functional Description
The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory
(SRAM) organized as 524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced
write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or read-modify-write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or
one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read
pipeline to clear. With NTD
™
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full
32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write
operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate
power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter
Input capacitance
I/O capacitance
* Guaranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
IN
= 0V
V
OUT
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
4/21/05, v 2.8
Alliance Semiconductor
P. 4 of 18
AS7C33512NTD32A/36A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
ZZ
NC
I/O Properties
I
I
I
I/O
I
I
I
I
I
I
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Description
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
This signal is internally pulled Low.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
4/21/05, v 2.8
Alliance Semiconductor
P. 5 of 18
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