s
mu @
MCS@51
8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Commercial/Express
8031AH18051AH18051AHP
8032N+18052N-I
8751W8751H-8
8751BW8752BI-I
s
High Performance HMOS Process
s
Internal Timers/Event Counters
s
2-Level interrupt Priority Structure
s
32 1/0 Lines (Four 8-Bit Ports)
s
64K External Program Memory Space
s
Security Feature Protects EPROM Parts
s
Boolean Processor
s
Bit-Addressable RAM
s
Programmable Full Duplex Serial
Channel
s
111 Instructions
(64
Single-Cycle)
s
s
Extended Temperature Range
64K External Data Memory Space
(–40”C to +85”C)
Against Software Piracy
The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can
be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a
Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The
8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROMless and-EPROM versions of each product.
Device
8031AH
8051AH
6051AHP
8751 H
8751 H-8
6751 BH
8032AH
6052AH
8752BH
Intsrnal Memory
Program
none
4K
X
8 ROM
4K
X
6 ROM
4K
X
8 EPROM
4K
X
8 EPROM
4K
X
8 EPROM
none
8K
X
8 ROM
8K
X
8 EPROM
Data
128
X
8 RAM
128
X
8 RAM
128
X
8 RAM
128
X
8 RAM
128
X
6 RAM
128
X
8 RAM
256
X
6 RAM
256
X
8 RAM
256
X
8 RAM
Timera/
Event Counters
2 x 18-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
3 x 16-Bit
3 x 16-Bit
3 x 16-Bit
Interrupts
5
5
5
5
5
5
6
6
6
I
Intel Corporationassumes no responsibility the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent
for
licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel.
O INTEL CORPORATION, 1994
October 1994
Order Numben 272318-002
MCS” 51
CONTROLLER
MO-M
7
P2.&P2 7
-
I
I
i
JK2U
1==4
~M
‘f2#fi+-oN,TMoD,TJ
Acc
fl
13
I
I
II
b
,,
,
STACK
POINTER
+1
L“
L-J
I
1
I
PSEN
ALE
‘%
“
TyG
g~
E
ml ... ,,
I
,
<>1
I
7’7
1
.
.
.. .
9
RST-+
i-
‘*
h-+ T
,,(-1
n
--% =2
I
II
P0nT3
119
LATCH
———————————
w
x
=
PI O*1 7
5
Pm
3
LHvI!RS
7
W
I
—..
—————
J
P] O-P3 7
272318-1
Figure 1. MCSI@ Controller Block Diagram
51
PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devic-
es are manufactured on P414.1, an HMOS II pro-
cess. The 8751H/8751 H-8 devices are manufac-
tured on P421.X, an HMOS-E process. The 8751BH
and 8752BH devices are manufactured on P422.
Additional process and reliability information is avail-
Q
able in Intel’s
Components
uality and Reliability
Handbook,
Order No, 210997.
MCS@ 51 CONTROLLER
PACKAGES
Part
8051AH
8031AH
8052AH
8032AH
6752BH*
8751H
8751 H-8
8051AHP
8751 BH
Prefix
P
D
N
Package Type
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
‘ja
Ojc
45°chV
4!5”CIW
46°C/W
16“C/W
15“CAIV
18°CfW
D
P
D
P
N
40-Pin CERDIP
40-Pin Plastic DIP
40-Pin CERDIP
40-Pin Plastic DIP
44-Pin PLCC
45”CIW
45”CIW
45°c/w
36”CIW
47”C1W
45“CIW
16°CfW
15“cf w
12°cf w
16”Cf W
NOTE:
*8752BH
is
36”/10” for D, and 38”/22” for N.
All thermal impedance data is approximate for static air conditions at IW of power dissipation. Values will
change depending on operating conditions and application. See the Intel Pac/raging
Handbook
(Order Number
240800) for a description of Intel’s thermal impedance test methodology.
~“52’80320NL’
L{
~
40
39
38
37
36
35
34
33
Vcc
P’,’ ADO
PO.1 AD1
PO.2 A02
PO.3 A03
PO.4 AD4
PO.5 AD5
P06 AD’
3 PO.7A07
3
EIJvpp”
Z
ALEIPROG”
3%FFI
3 P2.7 A15
2 P2.6A14
3 P2.5 A13
I P2.4 A12
1 P2.3 Al 1
> P2.2 AlO
3 P2 1 A9
X P20 A8
T2
T2EX
‘1
‘ss
+!--
29
26
27
26
25
24
23
22
21
EPROM only
q
“*Do
not connect
PI.’
P1.1
P1.2
P1.3
P1.4
P1.5
P1,6
P1.7
RST
RU2 P3.O
TXD P3.1
INTO P3.2
INT1 P3,3
TOP3 4
11 P3.5
~ P3.6
t% P3.7
XTAL2
XTAL1
I’__”ll
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
PI.6 ::8:;
P*,7 .:,.:
RST io;
(Rxo) P3.O :ji:
.1:;
:ji;
:!;;
:j:;
fTo) P3.4 :>!:
neaslvsd**
fTXD) P3.1
(INTo) P3.2
(INT1) P3.3
8X5X
272318-2
DIP
reserved
pins.
PLCC
Figure 2. MCS@51 Controller Connections
3
MCS” 51 CONTROLLER
w
PIN DESCRIPTIONS
Vcc: Supply voltage.
Vss: Circuit ground.
Port O:Port O is an 8-bit open drain bidirectional 1/0
port. As an output port each pin can sink 8 LS TTL
inputs.
Port Opins that have 1‘s written to them float, and in
that state can be used as high-impedance inputs.
Port O is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1‘s and can source and
sink 8 LS TTL inputs.
Port O also receives the code bytes during program-
ming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pullups are required during
program verification.
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
internal pullups, The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1‘s
written to them are pulled high by the internal pull-
UPS,and in that state can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
internal pullups.
Port 1 also receives the low-order address bytes
during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
In the 8032AH, 8052AH and 8752BH, Port 1 pins
P1.O and P1.1 also serve the T2 and T2EX func-
tions, respectively.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1‘s. Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri),Port 2 emits the contents of
the P2 Special Function Register.
Port 2 also receives the high-order address bits dur-
ing programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
The protection feature of the 8051AHP causes bits
P2.4 through P2.7 to be forced to O,effectively limit-
ing external Data and Code space to 4K each during
external accesses.
Port 3: Port 3 is an 8-bit bidirectional l/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1‘s
written to them are pulled high by the internal pull-
UPS,and in that state can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
pullups.
Port 3 also serves the functions of various special
features of the MCS 51 Family, as listed below:
Port
Pin
P3,0
P3.1
P3.2
P3,3
P3.4
P3.5
P3.6
P3.7
Alternative Function
RXD (serial input port)
TXD (serial output port)
INTO(external interrupt O)
INT1 (external interrupt 1)
TO(Timer Oexternal input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
~ (external data memory read strobe)
I
Port
Pin
P1
.0
P1.1
I
Alternative Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)
I
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice,
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during programming of the
EPROM parts.
In normal operation ALE is emitted at a constant
rate of 1/6the oscillator frequency, and may be used
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
Port 2: Port 2 is an 8-bit bidirectional l/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Porl 2 pins that have 1‘s
written to them are pulled high by the internal pull-
UPS,and in that state can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
internal pullups.
MCS” 51
CONTROLLER
w
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each ma-
chine cycle, except that two PSEN activations are
skipped during each access to external Data Memo-
ry
~/Vpp:
External Access enable ~
must be
strapped to VSS in order to enable any MCS 51 de-
vice to fetch code from external Program memory
locations starting at OOOOH to FFFFH. ~ must
up
be strapped to VCCfor internal program execution.
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.
This pin also receives the programming supply volt-
age (VPP) during programming of the EPROM parts.
C2
I
To drive the device from an external clock source,
XTAL1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
Vss
272318-3
Cl, C2 = 30 PF +10 PF for Crystals
For Ceramic Resonators contact resonatormanufacturer.
El
XTAL2
n
XTAL1
cl
Vss
=
272318-4
Figure 4. External Drive Configuration
EXPRESS Version
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
The EXPRESS program includes the commercial
standard temperature range with burn-in, and an ex-
tended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of O“C to + 70”C. With the ex-
tended temperature range option, operational char-
acteristics are guaranteed over a range of –40”C to
+ 85”C.
The optional burn-in is dynamic, for a minimum time
of 160 hours at 125°C with VCC = 5.5V * 0.25V,
following guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESSversions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
Figure 3. Oscillator Connections
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifi-
er,
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155; “Oscillators for Microcontrol-
Iers,” Order No, 230659.
I
5
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