Intel
®
80333 I/O Processor
Datasheet
Product Features
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Integrated Intel XScale
®
core
— 500, 667 and 800 MHz
— ARM* V5TE Compliant
— 32 KByte, 32-way Set Associative
Instruction Cache with cache locking
— 32 KByte, 32-way Set Associative Data
Cache with cache locking. Supports
write through or write back
— 2 KByte, 2-way Set Associative Mini-
Data Cache
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 4-Entry Fill and Pend Buffer
— Performance Monitor Unit
Internal Bus 333 MHz/64-bit
PCI Express*-to-PCI Bridges
— x8 PCI Express* Upstream Link
— PCI Express* Specification 1.0a
compliant
— PCI-X Bus A (IOP bus - ATU interface)
— PCI-X Bus B (Slot Expansion bus)
supports standard PCI Hot-Plug
Controller
— Four output clocks per PCI-X bus
Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
— Connects Internal Bus to PCI/X Bus A
— Messaging Unit and Expansion ROM
Two Programmable 32-bit Timers and
Watchdog Timer
Eight General Purpose I/O Pins
Two I
2
C Bus Interface Units
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Dual-Ported Memory Controller
— PC2700 Double Data Rate (DDR333)
SDRAM
— DDRII 400 SDRAM
— Up to 2 GB of 64-bit DDR333
— Up to 1 GB of 64-bit DDRII400
— Optional Single-bit Error Correction,
Multi-bit Detection Support (ECC)
— Supports Unbuffered or Registered
DIMMs and Discrete SDRAM
— 32-bit memory support
DMA Controller
— Two Independent Channels Connected
to Internal Bus
— Two 1KB Queues in Ch0 and Ch1
— CRC-32C Calculation
Application Accelerator Unit
— RAID6 support
— Performs optional XOR on Read Data
— Compute Parity Across Local Memory
Blocks
— 1 KB/512 byte Store Queue
Two UART (16550) Units
— 64-byte Receive and Transmit FIFOs
— 4-pin, Master/Slave Capable
Peripheral Bus Interface
— 8-/16-bit Data Bus with Two Chip Selects
Interrupt Controller Unit
— Four Priority Levels
— Vector Generation
— Sixteen External Interrupt Pins with
High Priority Interrupt (HPI#)
829-Ball, Flip Chip Ball Grid Array (FCBGA)
— 37.5 mm
2
and 1.27 mm ball pitch
Order Number: 305433, Revision: 003US
July 2005
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Copyright © 2005, Intel Corporation. All Rights Reserved.
July 2005
2
Intel
®
80333 I/O Processor Datasheet
Order Number: 305433, Revision: 003US
Datasheet
80333
Contents
1.0
Introduction....................................................................................................................................
7
1.1
About This Document ........................................................................................................... 7
1.1.1 Terminology ............................................................................................................. 7
1.1.2 Other Relevant Documents ..................................................................................... 8
About the Intel
®
80333 I/O Processor................................................................................... 9
Intel XScale
®
Core..............................................................................................................11
PCI Express*-to-PCI Bridge Units ......................................................................................11
Address Translation Unit ....................................................................................................12
Memory Controller ..............................................................................................................12
Application Accelerator Unit................................................................................................12
Peripheral Bus Interface .....................................................................................................12
DMA Controller ...................................................................................................................13
I
2
C Bus Interface Unit .........................................................................................................13
Messaging Unit ...................................................................................................................13
Internal Bus.........................................................................................................................13
UART Units .........................................................................................................................13
Interrupt Controller Unit ......................................................................................................14
GPIO ...................................................................................................................................14
SMBus Unit .........................................................................................................................14
Functional Signal Descriptions ...........................................................................................15
Package Thermal Specifications ........................................................................................55
Absolute Maximum Ratings ................................................................................................56
V
CCPLL
Pin Requirements...................................................................................................56
Targeted DC Specifications ................................................................................................57
Targeted AC Specifications ................................................................................................59
4.4.1 Clock Signal Timings .............................................................................................59
4.4.2 DDR/DDR-II SDRAM Interface Signal Timings......................................................61
4.4.3 Peripheral Bus Interface Signal Timings................................................................63
4.4.4 I
2
C/SMBus Interface Signal Timings......................................................................65
4.4.5 UART Interface Signal Timings..............................................................................65
4.4.6 PCI Express* Differential Transmitter (Tx) Output Specifications..........................66
4.4.7 PCI Express* Differential Receiver (Rx) Input Specifications ................................67
4.4.8 Boundary Scan Test Signal Timings......................................................................68
AC Timing Waveforms ........................................................................................................69
AC Test Conditions.............................................................................................................73
1.2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.0
3.1
3.2
4.0
4.1
4.2
4.3
4.4
Features........................................................................................................................................11
Package Information
...................................................................................................................15
Electrical Specifications
.............................................................................................................56
4.5
4.6
Figures
1
2
Intel
®
80333 I/O Processor Functional Block Diagram ...............................................................10
829-Ball FCBGA Package Diagram............................................................................................37
Datasheet
Intel
®
80333 I/O Processor Datasheet
Order Number: 305433, Revision: 003US
July 2005
3
80333
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Intel
®
80333 I/O Processor Signal Group Locations (Bottom View) ........................................... 38
Intel
®
80333 I/O Processor Ballout — Left Side (Bottom View) ................................................. 39
Intel
®
80333 I/O Processor Ballout — Right Side (Bottom View) ............................................... 40
Clock Timing Measurement Waveforms..................................................................................... 69
Output Timing Measurement Waveforms ................................................................................... 69
Input Timing Measurement Waveforms...................................................................................... 70
I
2
C/SMBus Interface Signal Timings .......................................................................................... 70
UART Transmitter Receiver Timing............................................................................................ 70
DDR SDRAM Write Timings ....................................................................................................... 71
DDR SDRAM Read Timings....................................................................................................... 71
Write PreAmble/PostAmble Durations........................................................................................ 72
AC Test Load for All Signals Except PCI and DDR SDRAM ...................................................... 73
AC Test Load for DDR SDRAM Signals ..................................................................................... 73
PCI/PCI-X TOV(max) Rising Edge AC Test Load ...................................................................... 73
PCI/PCI-X TOV(max) Falling Edge AC Test Load ..................................................................... 74
PCI/PCI-X TOV(min) AC Test Load ........................................................................................... 74
Transmitter Test Load (100
Ω
differential load) .......................................................................... 74
Transmitter Eye Diagram............................................................................................................ 75
Receiver Eye Opening (Differential) ........................................................................................... 75
Tables
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Pin Description Nomenclature .................................................................................................... 15
DDR SDRAM Signals ................................................................................................................. 16
MISC SDRAM Signals ................................................................................................................ 17
DDR-II SDRAM Signals .............................................................................................................. 17
Peripheral Bus Interface Signals ................................................................................................ 18
PCI Express* Signals ................................................................................................................. 19
B PCI (Slot Expansion) Bus Signals ........................................................................................... 20
A PCI (IOP) Bus Signals............................................................................................................. 22
I
2
C/SMBus Signals ..................................................................................................................... 24
Interrupt Signals ......................................................................................................................... 24
Hot-Plug Controller Signals for Parallel 1-slot, No-Glue ............................................................. 25
UART Signals ............................................................................................................................. 26
Test and Miscellaneous Signals ................................................................................................. 28
Reset Strap Signals .................................................................................................................... 29
Power and Ground Pins ............................................................................................................. 31
Pin Mode Behavior ..................................................................................................................... 32
Pin Multiplexing for Functional Modes ........................................................................................ 36
FC-style, H-PBGA Package Dimensions.................................................................................... 37
829-Lead Package — Alphabetical Ball Listings ........................................................................ 41
829-Lead Package — Alphabetical Signal Listings .................................................................... 48
Absolute Maximum Ratings ........................................................................................................ 56
Operating Conditions .................................................................................................................. 56
DC Characteristics...................................................................................................................... 57
I
CC
Characteristics...................................................................................................................... 58
PCI Clock Timings ...................................................................................................................... 59
DDR Clock Timings .................................................................................................................... 59
PCI Express* Clock Timings....................................................................................................... 60
DDR SDRAM Signal Timings ..................................................................................................... 61
July 2005
4
Intel
®
80333 I/O Processor Datasheet
Order Number: 305433, Revision: 003US
Datasheet
80333
29
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DDR-II SDRAM Signal Timings ..................................................................................................62
Peripheral Bus Signal Timings....................................................................................................63
PCI Signal Timings .....................................................................................................................64
I
2
C/SMBus Signal Timings .........................................................................................................65
UART Signal Timings .................................................................................................................65
PCI Express* Tx Output Specifications ......................................................................................66
PCI Express* Rx Input Specifications.........................................................................................67
Boundary Scan Test Signal Timings...........................................................................................68
AC Measurement Conditions......................................................................................................73
Datasheet
Intel
®
80333 I/O Processor Datasheet
Order Number: 305433, Revision: 003US
July 2005
5
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