AS7C25512NTD32A-100BC datasheet, PDF

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AS7C25512NTD32A-100BC: DescriptionZBT SRAM, 512KX32, 4ns, CMOS, PBGA119, 14 X 22 MM, BGA-119; Categorystorage storage; File Size51KB，2 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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AS7C25512NTD32A-100BC Overview

ZBT SRAM, 512KX32, 4ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

AS7C25512NTD32A-100BC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	LBGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	4 ns
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	16777216 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
organize	512KX32
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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• Organization: 524,288 words × 32 or 36 bits

• NTD

™

architecture for efficient bus operation

• Fast clock speeds to 200 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3/3.4/4 ns

• Fast OE access time: 3/3.4/4 ns

• Fully synchronous operation

• “Flow-through” or “pipelined” mode

• Asynchronous output enable control

• Economical 100-pin TQFP package

• 119 BGA (7 x 17 Ball Grid Array package)

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 2.5V core power supply

• 2.5V I/O operation

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

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A[18:0]

19

D

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Q

19

A

CE0

CE1

BWd

BWc

BWb

BWa

CE2

V

DD

V

SS

CLK

R/W

CEN

OE

ADV/LD

A

D

Q

19

DQPc, NC

DQc

V

DDQ

V

SSQ

DQc

V

SSQ

V

DDQ

DQc

FT

V

DD

V

DD

V

SS

DQd

V

DDQ

V

SSQ

DQd

V

SSQ

V

DDQ

DQd

DQPd, NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Address

register

Burst logic

CE0

CE1

CE2

R/W

BWa

BWb

BWc

BWd

ADV / LD

FT

LBO

ZZ

DQ [a:d]

36/32

Write delay

addr. registers

CLK

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

CLK

Control

logic

CLK

512K x 32

SRAM

Array

TQFP 14 x 20mm

D

Data

Q

Input

Register

CLK

36/32

CLK

CEN

CLK

OE

Output

Register

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb, NC

DQb

V

DDQ

V

SSQ

DQb

V

SSQ

V

DDQ

DQb

V

SS

V

DD

V

DD

ZZ

DQa

V

DDQ

V

SSQ

DQa

V

SSQ

V

DDQ

DQa

DQPa, NC

36/32

OE

DQ [a:d]

Note: Pins 1,30,51,80 are NC for ×32

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-200

Minimum cycle time

Maximum pipelined clock frequency

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

NTD

™

is a trademark of Alliance Semiconductor Corporation.

LBO

A

A1

A0

NC

V

SS

V

DD

NC

A

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Y

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Write Buffer

-166

6

166

3.4

230

70

30

-100

10

100

4.0

150

50

30

Units

ns

MHz

ns

mA

5

200

3.0

280

100

30

3 RI

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