Datasheet
V320USC Universal System Controller
PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface
• Glueless interface between popular MIPS™ and
SuperH™ processors and the standard 32-bit PCI bus
• Fully compliant with PCI 2.2 specification
• Configurable for primary master, bus master, or target
operation
• SDRAM controller with support for Enhanced SDRAM
• Up to 1 Kbyte burst access to (E)SDRAM from PCI,
32 bytes from local processor (MIPS mode)
• 640 bytes of on-chip FIFO storage with
Dynamic
Bandwidth Allocation™
architecture
• On-the-fly byte order (endian) conversion
• I
2
O Ready™ ATU and messaging unit
• Programmable chip select / peripheral device
strobe generation
• Hot Swap Ready (PICMG™ Hot Swap Specification 2.1)
• Implementation of PCI Bus Power Management Interface
Specification Version 1.0
• 3.3V operation with 5V tolerant inputs
• 208-pin PQFP package
• Up to 75 MHz local bus clock with separate
asynchronous PCI clock up to 50 MHz
• Two 32-bit timers
• Initialization through local processor, PCI or serial
EEPROM
Typical Application
V3 Semiconductor Corp.
2348G Walsh Avenue
Santa Clara, CA 95051
Phone (408) 988-1050, Fax (408) 988-2601
Toll Free (800) 488-8410 (US and Canada)
http://www.vcubed.com
Copyright © 1999 V3 Semiconductor Inc.
V320USC B1 Datasheet Rev 1.02 DS-UC01-0102
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V320USC Datasheet
Introduction
1.0 Introduction
The V320USC Universal System Controller simplifies the design of systems based on MIPS and SuperH microprocessors
by replacing many lower integration support components with a single, high-integration device. This saves design time,
board area, and manufacturing cost.
The I
2
O Ready V320USC from V3 Semiconductor is a high performance PCI bridge with integrated SDRAM controller for
MIPS processors operating at up to 75 MHz bus speed. It features address translation capabilities and large on-chip
buffers. A separate peripheral bus provides low latency access to SDRAM. The peripheral controller on the V320USC also
performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals.
The integrated SDRAM Controller connects the processor as well as the PCI bus through on-chip FIFOs to SDRAM arrays
of up to 1 Gbytes in size. The fully programmable SDRAM controller also supports the use of Enhanced SDRAM to achieve
even greater performance. Burst accesses of up to 1 Kbytes from PCI and 32 bytes from the MIPS processor are
supported.
The two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes
such as retriggerable or one-shot. The bus watch timer (MIPS mode) prevents system hangs during accesses to
undecoded regions. Interrupts for a real time OS can be easily generated by the system heartbeat timer. A watchdog timer
is also provided for graceful recovery from catastrophic program failures. Interrupt requests for all on-chip peripherals are
managed by the Interrupt Control Unit. Additionally, off-chip interrupts can be routed to the Interrupt Control Unit.
The V320USC is packaged in a low-cost 208-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 75 MHz speed
grade (MIPS mode), 66 MHz (SH mode).
This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC
characteristics for the V320USC. Detailed functional information is contained in the User’s Manual.
1.1
Listing of Figures
Figure 1: Pinout for 208-pin EIAJ PQFP in MIPS Mode (top view) . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2: Pinout for 208-pin EIAJ PQFP in SH3/4 Mode (top view) . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3: 208-pin EIAJ PQFP mechanical details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4: Clock and Synchronous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5: ALE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6: Serial EEPROM Waveforms and Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
14
15
19
19
21
1.2
Listing of Tables
Table 1: Product Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2: Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3: Signal Description—PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4: Signal Description—Local Bus Interface, MIPS™ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5: Signal Description—Local Bus Interface, SH3/4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6: Signal Description—DRAM and Peripheral Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7: Signal Description—Mode and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8: Signal Description—Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9: Signal Description—Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10: Pin Assignments for MIPS™ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
5
5
6
7
8
8
8
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V320USC B1 Datasheet Rev 1.02 DS-UC01-0102
Copyright © 1999 V3 Semiconductor Inc.
V320USC Datasheet
Product Code
Table 11: Pin Assignments for SH3/4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13: Guaranteed Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14: DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15: PCI Bus Signals DC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16: Local Bus/M Bus Signals DC Operating Specifications (VCC = 3.3V+ 0.3V) . . . . . . . . . .
Table 17: PCI Bus Signals AC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18: Local and M Bus AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19: M Bus AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 20: Capacitive Derating for Output and I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21: Local Bus/M-Bus Timing Parameters for Vcc =3.3 Volts +/- 5% . . . . . . . . . . . . . . . . . . . .
Table 22: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10% . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V3 Semiconductor retains the rights to change documentation, specifications, or
device functionality at any time without notice. Please verify that you have the latest copy
of all documents before finalizing a design.
10
15
16
16
16
17
17
18
18
19
19
20
21
2.0 Product Code
Table 1: Product Code
Product Code
V320USC-75 REV B1
Processors
MIPS (32-bit bus), SH3,
SH4 (32-bit bus)
Package
208-pin EIAJ PQFP
Frequency
75MHz
(66 MHz SH)
3.0 Pin Description
Table 2
lists the pin types found on the V320USC.
Table 2: Pin Types
Pin Type
PCI I
PCI O
PCI I/O
PCI I/OD
PCI input only pin.
PCI output only pin.
PCI tri-state I/O pin.
PCI input with open drain output.
Description
Copyright © 1999 V3 Semiconductor Inc.
V320USC B1 Datasheet Rev 1.02 DS-UC01-0102
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V320USC Datasheet
Pin Description
Table 2: Pin Types
Pin Type
I/O
2
,
I/O
8
,
I/O
12
I
O
2
,
O
8
,
O
12
Description
TTL I/O pins with 2/8/12 mA drive
TTL input only pin.
TTL output pins with 2/8/12 mA drive
3.1
Signal Description
The following tables describe the function of each pin on the V320USC.
Table 3: Signal Description—PCI Bus Interface
Signal
AD[31:0]
C/BE[3:0]
PAR
FRAME
Type
PCI I/O
PCI I/O
PCI I/O
PCI I/O
R
a
Z
Z
Z
Z
Description
Address and data, multiplexed on the same pins.
Bus Command and Byte Enables, multiplexed on the same pins.
Parity represents even parity across AD[31:0] and C/BE[3:0].
Cycle Frame indicates the beginning and burst length of an
access.
Initiator Ready indicates the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction.
Target Ready indicates the target agent’s (selected device’s)
ability to complete the current data phase of the transaction.
Stop indicates the current target is requesting the master to stop
the current transaction (retry or disconnect).
Device Select, when actively driven by a target, indicates the
driving device has decoded its address as the target of the current
access. As an input to the initiator, DEVSEL indicates whether
any device on the bus has been selected.
Initialization Device Select is used as a chip select during
configuration read and write transactions. It must be driven high in
order to access the chip’s internal configuration space.
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
IRDY
PCI I/O
Z
TRDY
PCI I/O
Z
STOP
PCI I/O
Z
DEVSEL
PCI I/O
Z
IDSEL
PCI I
PERR
PCI I/O
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V320USC B1 Datasheet Rev 1.02 DS-UC01-0102
Copyright © 1999 V3 Semiconductor Inc.
V320USC Datasheet
Pin Description
Table 3: Signal Description—PCI Bus Interface
Signal
Type
R
a
Description
System Error is used to report address parity errors, data parity
errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
Request indicates to the arbiter that this agent requests use of the
bus.
Grant indicates to the agent that access to the bus has been
granted.
PCLK provides timing for all transactions on the PCI bus.
SERR
PCI I/OD
Z
REQ
PCI O
Z
GNT
PCLK
PCI I
PCI I
a.
R
indicates state during reset.
Table 4: Signal Description—Local Bus Interface, MIPS™ Mode
Signal
SYSAD[31:0]
SYSCMD[8:0]
Type
I/O
I/O
R
Z
Z
Description
System Address / Data (multiplexed)
System Command / data identifier. When MODE0 = ‘0’,
SYSCMD[8:5] should be pulled high.
Valid command or data from external agent. This signal should
have an external pull-up resistor.
Valid command or data from MIPS™
Release the system interface to slave state
Z
Write Ready: this signal should have an external pull-up resistor.
Local clock
VALIDIN
VALIDOUT
RELEASE
WRRDY
LCLK
O
8
I
I
O
8
I
Z
Table 5: Signal Description—Local Bus Interface, SH3/4 Mode
Signal
A[31:26]/
CS[5:0]
A[25:0]
D[31:0]
RD/WR
Type
I/O
8
I
I/O
8
I/O
8
I/O
8
R
Z
Upper System Address
Lower System Address
Data Bus
Read/not Write. This is also referred to as MWE for SDRAM
Description
Z
Z
Z
Copyright © 1999 V3 Semiconductor Inc.
V320USC B1 Datasheet Rev 1.02 DS-UC01-0102
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