UBA2080/1
Half-bridge driver IC
Rev. 1.1 — 6 December 2011
Objective data sheet
1. General description
The UBA2080 and UBA2081 are high voltage monolithic integrated circuits made using
the latch-up free Silicon-On-Insulator (SOI) process. The circuit is designed for driving
MOSFETs in a half-bridge configuration.
2. Features and benefits
Integrated half-bridge driver circuit
Integrated bootstrap diode
Maximum voltage of 600 V
Output driver capability: I
O(sink)
= 400 mA and I
O(source)
= 200 mA
Maximum frequency 800 kHz
UBA2080:
Outputs in phase with inputs
UBA2081:
Adjustable dead-time
Shutdown input
3. Applications
Driver (via external MOSFETs) for any kind of load in a half-bridge configuration
4. Ordering information
Table 1.
Ordering information
Package
Name
UBA2080P
UBA2081P
UBA2080T
UBA2081T
UBA2080AT
SO14
plastic small outline package; 14 leads
SOT108-1
SO8
plastic small outline package; 8 leads
SOT96-1
DIP8
Description
plastic dual in-line package; 8 leads
Version
SOT97-1
Type number
NXP Semiconductors
UBA2080/1
Half-bridge driver IC
5. Block diagram
FS
V
DD
ULVO
ULVO
R1
R2 S
HS DRIVER
GH
HIN
LOGIC
LEVEL SHIFTER
SH
LIN
LS DRIVER
GL
GND
aaa-001102
Fig 1.
Block diagram (UBA2080X)
FS
V
DD
ULVO
ULVO
R1
R2 S
HS DRIVER
GH
CLK
LOGIC
LEVEL SHIFTER
SH
SD
NON-OVERLAP
LS DRIVER
GL
GND
V
ref
aaa-001107
Fig 2.
Block diagram (UBA2081X)
Refer to
Figure 7 “Typical UBA2080X application”
and
Figure 8 “Typical UBA2081X
application”
for detailed information on the required application components.
UBA2080_UBA2081
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 6 December 2011
2 of 15
NXP Semiconductors
UBA2080/1
Half-bridge driver IC
6. Pinning information
6.1 Pinning
GND
GND
SD/LIN
V
DD
GND
LIN
HIN
1
2
3
4
aaa-001121
1
2
3
4
5
6
7
aaa-001134
14 SEL
13 GND
12 V
DD
8
GL
SH
GH
FS
GND
CLK/HIN
FS
GH
UBA2080AT
11 GL
10 GND
9
8
GND
SH
V
DD
GND
SD
CLK
1
2
3
4
aaa-001126
8
GL
SH
GH
FS
UBA2080
7
6
5
UBA2081
7
6
5
Fig 3.
UBA2080X: Pin
configuration DIP8 and
SO8 package
Fig 4.
UBA2080AT: Pin
configuration SO14
package
Fig 5.
UBA2081X: Pin
configuration DIP8 and
SO8 package
6.2 Pin description
Table 2.
Symbol
Pin description UBA2080X/1X DIP8 and SO8
Pin
UBA2080X
(DIP8/SO8)
V
DD
GND
LIN
SD
HIN
CLK
FS
GH
SH
GL
Table 3.
Symbol
GND
SD/LIN
CLK/HIN
FS
SH
GH
1
2
3
-
4
-
5
6
7
8
-
3
-
4
UBA2081X
(DIP8/SO8)
IC supply
IC ground and low-side driver return
low-side driver logic input
low-side driver logic input
high-side driver logic input
high-side driver logic input
floating supply voltage
high-side MOSFET gate
high-side MOSFET source
low-side MOSFET gate
Description
Pin description UBA2080AT (SO14)
Pin
1, 2, 4, 9, 10, 13
3
5
6
8
7
Description
IC ground and low side driver return
low-side driver logic input
high-side driver logic input
floating supply voltage
high-side MOSFET source
high-side MOSFET gate
UBA2080_UBA2081
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 6 December 2011
3 of 15
NXP Semiconductors
UBA2080/1
Half-bridge driver IC
Pin description UBA2080AT (SO14)
…continued
Pin
11
12
14
Description
low-side MOSFET gate
IC supply
select UBA2080 or UBA2081 functionality
Table 3.
Symbol
GL
V
DD
SEL
7. Functional description
7.1 Start-up state
The IC enters the start-up state when the supply voltage on pin V
DD
increases. In the
start-up state, the high-side power transistor is non-conducting and the low-side power
transistor is switched on. The internal circuit is reset and the capacitor on the bootstrap pin
FS is charged. The start-up state is defined until the value of V
DD
= the V
DD(start)
value.
After which the IC switches to the oscillation state.
The circuit enters the start-up state again when the voltage on pin V
DD
V
DD(stop)
.
7.2 UBA2080 oscillation state
In the oscillation state, the output voltage of the GL and GH drivers depend on the logical
signals HIN and LIN, see
Table 4
To prevent cross conduction in the half-bridge MOSFETs, the combination HIN = LIN = 1
is not allowed. Both GL and GH are LOW under this condition.
Table 4.
State
Start-up
Oscillation
Oscillation
Oscillation
Oscillation
logic table
HIN
-
0
0
1
1
LIN
-
0
1
0
1
GL
HIGH
LOW
HIGH
LOW
LOW
GH
LOW
LOW
LOW
HIGH
LOW
7.3
UBA2081 oscillation state
In the oscillation state, the output voltage of the GL and GH drivers depend on the logical
signals CLK and SD, see
Table 5
Table 5.
State
Start-up
Oscillation
Oscillation
Oscillation
Oscillation
logic table
CLK
-
0
1
0
1
SD
-
0
0
1
1
GL
HIGH
HIGH
LOW
LOW
LOW
GH
LOW
LOW
HIGH
LOW
LOW
UBA2080_UBA2081
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 6 December 2011
4 of 15
NXP Semiconductors
UBA2080/1
Half-bridge driver IC
7.4 UBA2081 non-overlap time
The external resistor (R
SD
) on pin SD sets the non-overlap time of the UBA2081. The
relationship between this resistor value and actual dead-time is listed in
Figure 6.
3000
t
no
(ns)
2000
aaa-001135
1000
0
0
1
2
R
SD
(MΩ)
3
Fig 6.
Non-overlap time versus SD resistor (R
SD
)
UBA2080_UBA2081
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 6 December 2011
5 of 15
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