19-6078; Rev 11/11
1024K NV SRAM with Phantom Clock
FEATURES
DS1248/DS1248P
Real-Time Clock (RTC) Keeps Track of
Hundredths of Seconds, Minutes, Hours,
Days, Date of the Month, Months, and Years
128K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM
Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data
Watch Function is Transparent to RAM
Operation
Automatic Leap Year Compensation Valid
Up to 2100
Full 10% Operating Range
Over 10 Years of Data Retention in the
Absence of Power
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only
Standard 32-Pin JEDEC Pinout
PIN CONFIGURATIONS
TOP VIEW
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
DS1248
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
N.C.
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Encapsulated DIP
(740-mil Flush)
Underwriters Laboratories (UL) Recognized
(www.maxim-ic.com/qa/info/ul/)
PowerCap Module Board Only
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Pin-for-Pin Compatible with DS1244P and
DS1251P
RST
A15
A16
N.C.
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1248P
X1
GND
V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap Module Board
(Uses DS9034PCX+ PowerCap)
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
ORDERING INFORMATION
PART
DS1248Y-70+
DS1248Y-70IND+
DS1248YP-70+
DS1248W-120+
DS1248W-120IND+
DS1248WP-120+
DS1248WP-120IND+
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
V
CC
RANGE
5V ±10%
5V ±10%
5V ±10%
3.3V ±10%
3.3V ±10%
3.3V ±10%
3.3V ±10%
PIN-PACKAGE
32 EDIP
32 EDIP
34 PowerCap*
32 EDIP
32 EDIP
34 PowerCap*
34 PowerCap*
+ Denotes a lead(Pb)-free/RoHS-compliant package.
*
DS9034PCX+ or DS9034I-PCX+ (PowerCap) required. Must be ordered separately.
DETAILED DESCRIPTION
The DS1248 1024K NV SRAM with phantom clock is a fully static, nonvolatile RAM (organized as
128K words by 8 bits) with a built-in real-time clock. The DS1248 has a self-contained lithium energy
source and control circuitry, which constantly monitors V
CC
for an out-of-tolerance condition. When such
a condition occurs, the lithium energy source is automatically switched on and writes protection is
unconditionally enabled to prevent garbled data in both the memory and real-time clock.
PACKAGES
The DS1248 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1248P after completion of the surface mount process. Mounting the PowerCap after the surface mount
process prevents damage to the crystal and battery because of the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
are ordered separately and shipped in separate containers.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PIN DESCRIPTION
PIN
EDIP PowerCap
1
2
3
4
5
6
7
8
9
10
11
12
23
25
26
27
28
31
13
14
15
17
18
19
20
21
22
24
29
30
32
16
1
3
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
2
16
15
14
13
12
11
10
9
8
7
6
4, 33, 34
5
17
NAME
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
A8
A13
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
OE
WE
N.C.
V
CC
GND
FUNCTION
Active-Low Reset Input. This pin has an internal pullup resistor
connected to V
CC
.
Address Inputs
Data In/Data Out
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
No Connect
Power-Supply Input
Ground
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
The DS1248 executes a read cycle whenever
WE
(write enable) is inactive (high) and
CE
(chip enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within t
ACC
(access time) after the last address input signal is stable, providing that
CE
and
OE
(output enable) access
times and states are also satisfied. If
OE
and
CE
access times are not satisfied, then data access must be
measured from the later occurring signal (CE or
OE)
and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE,
rather than address access.
The DS1248 is in the write mode whenever the
WE
and
CE
signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CEor WE.
All address inputs must
be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and
OE
active)
then
WE
will disable the outputs in t
ODW
from its falling edge.
The 5V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point, V
PF
(point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point, V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
BAT
, the device power is
switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below V
PF
. If V
PF
is greater than V
BAT
,
the device power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below V
BAT
. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered-down.
RAM READ MODE
RAM WRITE MODE
DATA RETENTION MODE
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the
CE
and
OE
control of the phantom clock starts the pattern recognition sequence by moving a pointer to
the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CE
and
WE
control of the SmartWatch. These 64 write cycles are used only to gain access to the phantom
clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles
generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The
preferred
way
to
manage
this
requirement
is
to
set
aside
just
one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is
compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next
location of the comparison register and awaits the next write cycle. If a match is not found, the pointer
does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during
pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and
data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom
clock to either receive or transmit data on DQ0, depending on the level of the
OE
pin or the
WE
pin.
Cycles to other locations outside the memory block can be interleaved with
CE
cycles without
interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
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