PRELIMINARY
EZ-PD™ CCG3
USB Type-C Port Controller
General Description
EZ-PD™ CCG3 is a highly integrated USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD
CCG3 provides a complete USB Type-C and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking
stations and power adapters. CCG3 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM
®
Cortex
®
-M0 processor
with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant
regulator, and a pair of FETs to switch a 5V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to
control external VBUS FETs and system level ESD protection. CCG3 is available in 40-QFN, 32-QFN, and 42-WLCSP packages.
Features
Type-C and USB-PD Support
Integrated USB Power Delivery 3.0 support
■
Integrated USB-PD BMC transceiver
■
Integrated VCONN FETs
■
Configurable resistors R
A
, R
P
and R
D
■
Dead Battery Detection support
■
Integrated fast role swap and extended data messaging
■
Supports one USB Type-C port
■
Integrated Hardware based overcurrent protection (OCP) and
overvoltage protection (OVP)
■
Clocks and Oscillators
■
Integrated oscillator eliminating the need for external clock
Power
■
■
■
■
2.7 V to 21.5 V operation
2x Integrated dual-output gate drivers for external VBUS FET
switch control
Independent supply voltage pin for GPIO that allows 1.71 V to
5.5 V signaling on the I/Os
Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
On CC, SBU, DPLUS, DMINUS and VBUS pins
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
System-Level ESD Protection
■
■
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU
■
128-KB Flash
■
8-KB SRAM
■
Packages
■
■
Integrated Digital Blocks
Hardware Crypto block enables Authentication
■
Full-Speed USB Device Controller supporting Billboard Device
Class
■
Integrated timers and counters to meet response times
required by the USB-PD protocol
■
Four run-time reconfigurable serial communication blocks
(SCBs) with reconfigurable I
2
C, SPI, or UART functionality
■
40-pin QFN, 32-pin QFN, and 42-ball CSP for
Notebooks/Accessories
Supports industrial temperature range (–40 °C to +105 °C)
Cypress Semiconductor Corporation
Document Number: 002-03288 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 26, 2016
PRELIMINARY
EZ-PD™ CCG3
Logic Block Diagram
Document Number: 002-03288 Rev. *G
Page 2 of 43
PRELIMINARY
EZ-PD™ CCG3
Contents
EZ-PD CCG3 Block Diagram ............................................ 4
Functional Overview ........................................................ 5
CPU and Memory Subsystem ..................................... 5
Crypto Block ................................................................ 5
Integrated Billboard Device ......................................... 5
USB-PD Subsystem (USBPD SS) .............................. 5
Full-Speed USB Subsystem ........................................ 6
Peripherals .................................................................. 6
GPIO ........................................................................... 7
Power Systems Overview ................................................ 8
Pinouts .............................................................................. 9
Available Firmware and Software Tools ....................... 13
EZ-PD Configuration Utility ....................................... 13
CCG3 Programming and Bootloading .......................... 14
Programming the Device Flash
over SWD Interface ................................................... 14
Application Firmware Update
over Specific Interfaces (I2C, CC, USB) .................... 14
Applications .................................................................... 17
Electrical Specifications ................................................ 23
Absolute Maximum Ratings ....................................... 23
Device-Level Specifications ...................................... 24
Digital Peripherals ..................................................... 26
System Resources .................................................... 28
Ordering Information ...................................................... 33
Ordering Code Definitions ......................................... 33
Packaging ........................................................................ 34
Acronyms ........................................................................ 37
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
References and Links to Applications Collaterals ..... 39
Document History Page ................................................. 40
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Document Number: 002-03288 Rev. *G
Page 3 of 43
PRELIMINARY
EZ-PD™ CCG3
EZ-PD CCG3 Block Diagram
Figure 1. EZ-PD CCG3 Block Diagram
[1]
CPU Subsystem
CCG3
32-bit
SWD/TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
2x64 KB
Read Accelerator
SRAM
8 KB
SRAM Controller
ROM
8 KB
ROM Controller
AHB-Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
System Interconnect (Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
USB-PD SS
IOSS GPIO (3 x ports)
4 x TCPWM
USB-FS
CRYPTO
4 x SCB
2 x 2 ANALOG XBAR
2 X GATE DRIVER
2 X VCONN FET
CC BB PHY
Power Modes
Active/Sleep
Deep Sleep
High Speed I/O Matrix
22 x GPIOs, 2 x OVTs
Pads, ESD
ADC / ACA
CHG DET
HV REG
OVP
OCP
FS-PHY
IO Subsystem
Note
1. See
Acronyms
section for more details.
Document Number: 002-03288 Rev. *G
Page 4 of 43
PRELIMINARY
EZ-PD™ CCG3
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in EZ-PD CCG3 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a two-wire form of JTAG. The debug configuration used
for EZ-PD CCG3 has four break-point (address) comparators
and two watchpoint (data) comparators.
Flash
The EZ-PD CCG3 device has a flash module with two banks of
64 KB flash, a flash accelerator, tightly coupled to the CPU to
improve average access times from the flash block. The flash
block is designed to deliver 1 wait-state (WS) access time at
48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
USB-PD Subsystem (USBPD SS)
The USB-PD sub-system contains all of the blocks related to
USB Type-C and Power Delivery. The sub-system is comprised
of the following:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
BMC PHY: USB-PD Transceiver with Fast Role Swap (FRS)
transmit and detect
VCONN power FETs for the CC lines
VCONN Ra Termination and Leakers
Analog Cross-Bar to switch between the SBU1/SBU2 and
AUX_P/AUX_N pins
Programmable Pull-up and Pull-down termination on the
AUX_P/AUX_N pins
HPD Processor
VBUS_C Regulator (20V LDO)
Power Switch between VSYS supply and VBUS_C Regulator
output
VBUS_C Over-Voltage
Detectors
(OV)
and
Under-Voltage
(UV)
Current Sense Amplifier (CSA) for over current detection
Gate Drivers for VBUS_P and VBUS_C external Power FETs
VBUS_C discharge switch
USB2.0 Full-Speed (FS) PHY with integrated 5.0V to 3.3V
regulator
Charger Detection / Emulation for USB BC1.2 and other
proprietary protocols
2 instances of 8-bit SAR ADCs
8kV IEC ESD Protection on the following pins: VBUS_C, CC1,
CC2, SBU1, SBU2, DP, DM
Crypto Block
CCG3 integrates a crypto block for hardware assisted
authentication of firmware images. It also supports field
upgradeability of firmware in a trusted ecosystem. The CCG3
Crypto block provides cryptography functionality. It includes
hardware acceleration blocks for AES (Advanced Encryption
Standard) block cipher, SHA-1 (Secure Hash Algorithm) and
SHA-2 hash, Cyclic Redundancy Check (CRC) and pseudo
random number generation.
Integrated Billboard Device
CCG3 integrates a complete full speed USB 2.0 device controller
capable of functioning as a Billboard class device. The USB 2.0
device controller can also support other device classes.
The EZ-PD™ CCG3 USB-PD subsystem interfaces to the pins
of a USB Type-C connector. It includes a USB Type-C baseband
transceiver and physical-layer logic. This transceiver performs
the BMC and the 4b/5b encoding and decoding functions as well
as integrating the 1.2V analog front end. This subsystem
integrates the required terminations to identify the role of the
CCG3 device, including Rp and Rd for UFP/DFP roles and Ra
for EMCA/VCONN powered accessories. The programmable
VCONN leakers are included in order to discharge VCONN
capacitance during a disconnect event. It also integrates power
FETs for supplying VCONN power to the CC1/CC2 pins from the
V5V pin. The Analog Cross-Bar allows for connecting either of
the SBU1/SBU2 pins to either of the AUX_P/AUX_N pins to
support DisplayPort sideband signaling. The integrated HPD
processor can be used to control or monitor the HPD signal of a
DisplayPort source or sink.
Document Number: 002-03288 Rev. *G
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