...................................................................................................................................-65 to 150¡C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183¡C, 230¡C peak
Lead Symbol
Lead Name
V
MAX
5.5V
5.5V
5.5V
5.5V
7.5V
5.5V
20V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V DC,
-2.0V for
t < 50ns
0V
0V
-0.3V
-0.3V
-0.3V
I
SOURCE
5 mA
1mA
1mA
N/A
2mA
1mA
200mA DC,
1A peak
(t < 100µs)
25 mA
1A Peak,
200mA DC
1mA
150mA
(short circuit)
N/A
I
SINK
5 mA
1mA
1mA
N/A
50mA
1mA
200mA DC,
1A peak
(t < 100µs)
N/A
N/A
N/A
5mA
200mA DC,
1A peak
(t < 100µs)
SYNC
CT
RT
V
FB1
, V
FB2
COMP1, COMP2
V
FFB1
, V
FFB2
GATE1, GATE2
Oscillator Synchronization Input
Oscillator Integrating Capacitor
Oscillator Charge Current Resistor
Voltage Feedback Inputs
Error Amplifier Outputs
PWM Ramp Inputs
FET Gate Drive Outputs
LGnd
PGnd
ENABLE
V
REF
V
IN
Reference Ground and IC Substrate
Power Ground
Channel 2 Enable
Reference Voltage Output
Power Supply Input
0V
0V
5.5V
5.5V
20V
Electrical Characteristics: 0¡C < T
A
< 70¡C; 0¡C < T
J
< 125¡C; 9.4V < V
IN
< 20V; C
T
= 330 pF; R
T
= 27k½;
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Reference Section
V
REF
Output Voltage
Line Regulation
Load Regulation
V
REF
Variation over Line, Load
and Temperature
Output Short Circuit Current
s
Oscillator Section
Oscillator Frequency Variation
over Line and Temperature
Maximum Duty Cycle
Sync Threshold
Sync Bias Current
Sync Propagation Delay
175
80
0.8
V
SYNC
= 2.4V
V
SYNC
= 5.0V
210
90
1.6
170
430
230
245
98
2.4
250
750
kHz
%
V
µA
ns
1 mA < I
VREF
< 10 mA
4.85
30
100
Room Temperature,
I
VREF
= 1mA, V
IN
= 12V
4.9
5.0
1
15
5.1
20
26
5.15
150
V
mV
mV
V
mA
2
CS5127
Electrical Characteristics: 0¡C < T
A
< 70¡C; 0¡C < T
J
< 125¡C; 9.4V < V
IN
< 20V; C
T
= 330 pF; R
T
= 27k½;
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Error Amplifiers
V
FB
Reference Voltage
Input Bias Current
Open Loop Gain
Unity Gain Bandwidth
PSRR
COMP Source Current
COMP Sink Current
COMP Output Low Voltage
s
PWM Comparators
V
FFB
Bias Current
Propagation Delay
Common Mode
Maximum Input Voltage
s
ENABLE Lead
ENABLE High Threshold
ENABLE Bias Current
s
Gate Driver Outputs
Output Low Saturation Voltage
Output High Saturation Voltage
Output Voltage under Lockout
Output Rise Time
Output Fall Time
s
Undervoltage Lockout
Turn On Threshold
Turn Off Threshold
s
Supply Current
Start Up Current
Operating Current
V
COMP
= V
VFB
V
FB
= 1.275V
1.245
f = 120Hz
V
COMP
= 3V, V
VFB
= 1.1V
V
COMP
= 1.2V, V
VFB
= 1.45V
V
VFB
= 1.45V, I
COMP
= 0.3 mA
0.9
10
0.50
1.275
0.1
85
1.0
80
1.3
16
0.85
1.300
1.0
2.0
24
1.00
V
µA
dB
MHz
dB
mA
mA
V
V
FFB
= 0
V
FFB
rising to V
GATE
falling
2.9
2.0
100
3.3
20
250
µA
ns
V
channel 2 enabled
V
ENABLE
= 0
1.5
100
2.5
250
3.5
400
V
µA
I
GATE
= 20 mA
I
GATE
= 100 mA
I
GATE
= 20 mA
I
GATE
= 100 mA
V
IN
= 6V, I
GATE
= 1 mA
no load
no load
0.1
0.25
1.5
1.6
0.1
30
10
0.4
2.50
2.0
3.0
0.2
V
V
V
V
V
ns
ns
7.4
6.8
8.4
7.8
9.4
8.8
V
V
V
IN
= 6V
V
CT
= 0V, no load
0.4
17.5
0.8
25
mA
mA
3
CS5127
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
16 Lead SO Wide
1
SYNC
A pulse train on this lead will synchronize the oscillator. Sync threshold level
is 2.4V. Synchronization frequency should be at least 10% higher than the reg-
ular operating frequency. The sync feature is level sensitive.
The oscillator integrating capacitor is connected to this lead.
The oscillator charge current setting resistor is connected to this lead.
The inverting input of the channel 1 error amplifier is brought out to this lead.
The lead is connected to a resistor divider which provides a measure of the
output voltage. The input is compared to a 1.275V reference, and channel 1
error amp output is used as the V
2
ª PWM control voltage.
Channel 1 error amp output and PWM comparator input.
This lead connects to the non-inverting input of the channel 1 PWM comparator.
This lead is the gate driver for the channel 1 FET. It is capable of providing
nearly 1A of peak current.
This lead provides a ÒquietÓ ground for low power circuitry in the IC. This
lead should be shorted to the PGND lead as close as possible to the IC for best
operating results.
This lead is the power ground. It provides the return path for the FET gate dis-
charge. It should be shorted to the LGND lead as close as possible to the IC for
best operating results.
This lead is the gate driver for the channel 2 FET. See GATE1 lead description
for more details.
This lead connects to the non-inverting input of the channel 2 PWM comparator.
Channel 2 error amp output and PWM comparator input.
Inverting input for the channel 2 error amp. See V
FBI
for more details.
The regulator controlled by channel 2 may be turned on and off selectively by
the user. Pulling the ENABLE lead above 3.5V will turn channel 2 on. Setting
the ENABLE lead voltage below 1.5V guarantees that channel 2 is off.
This lead is the output of a ± 3% reference. This reference drives most of the
on-chip circuitry, but will provide a minimum of 10 mA to external circuitry if
needed. The reference is inherently stable and does not require a compensa-
tion capacitor, but use of a decoupling capacitor will reduce noise in the IC.
This lead is the power supply input to the IC. The maximum input voltage
that can be withstood without damage to the IC is 20V.
2
3
4
C
T
R
T
V
FB1
5
6
7
8
COMP1
V
FFB1
GATE1
LGND
9
PGND
10
11
12
13
14
GATE2
V
FFB2
COMP2
V
FB2
ENABLE
15
V
REF
16
V
IN
4
CS5127
Block Diagram
COMP1
V
FFB1
+
V
FB1
1.275V
-
Error
Amplifier
PWM
Comparator
-
+
Bandgap
Voltage
Reference
Channel 2
Gate Driver
GATE1
V
REF
V
IN
SYNC
R
T
C
T
V
FB2
1.275V
V
IN
Undervoltage
Lockout
Reference
Undervoltage
Lockout
LGND
PGND
Oscillator
+
Error
Amplifier
Channel 2
Gate Driver
-
PWM
Comparator
GATE2
-
+
COMP2
V
FFB2
ENABLE
Theory of Operation
The CS5127 is a dual power supply controller that utilizes
the V
2
ª control method. Two nonsynchronous V
2
ª buck
regulators can be built using a single controller IC. This IC
is a perfect choice for efficiently and economically provid-
ing core power and I/O power for the latest
high-performance CPUs. Both switching regulators
employ a fixed frequency architecture driven from a
common oscillator circuit.
V
2
ª Control Method
The V
2
ª method of control uses a ramp signal generated
by the ESR of the output capacitors. This ramp is propor-
tional to the AC current in the inductor and is offset by the
DC output voltage. V
2
ª inherently compensates for varia-
tion in both line and load conditions since the ramp signal
is generated from the output voltage. This differs from tra-
ditional methods such as voltage mode control, where an
artificial ramp signal must be generated, and current mode
control, where a ramp is generated from inductor current.
The V
2
ª control method is illustrated in Figure 1. Both
the ramp signal and the error signal are generated by the
output voltage. Since the ramp voltage is defined as the
output voltage, the ramp signal is affected by any change
in the output, regardless of the origin of that change. The
ramp signal also contains the DC portion of the output
voltage, allowing the control circuit to drive the output
switch from 0% to about 90% duty cycle.
Changes in line voltage will change the current ramp in
the inductor, affecting the ramp signal and causing the
V
2
ª control loop to adjust the duty cycle. Since a change
in inductor current changes the ramp signal, the V
2
ª
method has the characteristics and advantages of current
mode control for line transient response.
Changes in load current will affect the output voltage and
thus will also change the ramp signal. A load step will
immediately change the state of the comparator output
that controls the output switch. In this case, load transient
response time is limited by the comparator response time
and the transition speed of the switch. Notice that the reac-
tion time of the V
2
ª loop to a load transient is not
dependent on the crossover frequency of the error signal
loop. Traditional voltage mode and current mode methods
are dependent on the compensation of the error signal
loop.
The V
2
ª error signal loop can have a low crossover fre-
quency, since transient response is handled by the ramp
signal loop. The ÒslowÓ error signal loop provides DC
accuracy. Low frequency roll-off of the error amplifier
bandwidth will significantly improve noise immunity.
This also improves remote sensing of the output voltage,
since switching noise picked up in long feedback traces
can be effectively filtered.
V
2
ª line and load regulation are dramatically improved
because there are two separate control loops. A voltage
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