MT49H16M18CHU-25 datasheet, PDF

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MT49H16M18CHU-25: DescriptionDDR DRAM, 16MX18, 0.25ns, CMOS, PBGA144, FBGA-144; Categorystorage storage; File Size2MB，68 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT49H16M18CHU-25 Overview

DDR DRAM, 16MX18, 0.25ns, CMOS, PBGA144, FBGA-144

MT49H16M18CHU-25 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	BGA
package instruction	FBGA-144
Contacts	144
Reach Compliance Code	not_compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.25 ns
Other features	AUTO REFRESH
Maximum clock frequency (fCLK)	400 MHz
I/O type	SEPARATE
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B144
JESD-609 code	e0
length	18.5 mm
memory density	301989888 bit
Memory IC Type	DDR DRAM
memory width	18
Number of functions	1
Number of ports	1
Number of terminals	144
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
organize	16MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA144,12X18,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	235
power supply	1.5/1.8,1.8,2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.026 A
Maximum slew rate	0.97 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Terminal surface	TIN LEAD SILVER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	11 mm

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288Mb: x18 2.5V V

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Features

SIO

RLDRAM

MT49H16M18C – 16 Meg x 18 x 8 banks

Features

• 400 MHz DDR operation (800 Mb/s/pin data rate)

• 28.8 Gb/s peak bandwidth (x18 at 400 MHz clock

frequency)

• Organization

–

16 Meg x 18 separate I/O

–

8 banks

• Cyclic bank switching for maximum bandwidth

• Reduced cycle time (20ns at 400 MHz)

• Nonmultiplexed addresses (address multiplexing

option available)

• SRAM-type interface

• Programmable READ latency (RL), row cycle time,

and burst sequence length

• Balanced READ and WRITE latencies in order to

optimize data bus utilization

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Differential input data clocks (DKx, DKx#)

• On-die DLL generates CK edge-aligned data and

output data clock signals

• Data valid signal (QVLD)

• 32ms refresh (8K refresh for each bank; 64K refresh

command must be issued in total each 32ms)

• 144-ball µBGA package

• HSTL I/O (1.5V or 1.8V nominal)

• 25–60Ω matched impedance outputs

• 2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

Q I/O

• On-die termination (ODT) R

Figure 1:

144-Ball µBGA

Options

• Clock cycle timing

–

2.5ns (400 MHz)

–

3.3ns (300 MHz)

–

5ns (200 MHz)

• Configuration

–

16 Meg x 18

• Operating temperature range

–

Commercial (0° to +95°C)

–

Industrial (T

= –40°C to +95°C;

= –40°C to +85°C)

• Package

–

144-ball µBGA

–

144-ball µBGA (Pb-free)

–

144-ball FBGA

–

144-ball FBGA (Pb-free)

Marking

-25

-33

-5

16M18

None

2, 3

Notes: 1. Contact Micron for availability of industrial

temperature products.

2. Contact Micron for availability of Pb-free

products.

3. The FBGA package is being phased out.

PDF: 09005aef815b2df8/Source: 09005aef811ba111

288Mb_RLDRAM_II_SIO_D1.fm - Rev. O 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

288Mb: x18 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Table of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical Specifications – I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Electrical Specifications – AC and DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

AC and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Input Slew Rate Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

AUTO REFRESH (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

PDF: 09005aef815b2df8/Source: 09005aef811ba111

288Mb_RLDRAM_II_SIOTOC.fm - Rev. O 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

288Mb: x18 2.5V V

EXT

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List of Figures

Figure 1:

Figure 2:

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Figure 30:

Figure 31:

Figure 33:

Figure 35:

Figure 36:

Figure 37:

Figure 38:

Figure 39:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

288Mb RLDRAM II SIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

16 Meg x 18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Nominal tAS/

CS/

DS and tAH/

CH/

DH Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Mode Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Mode Register Definition in Nonmultiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Read Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Power-Up/Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Power-Up/Initialization Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Consecutive READ Bursts (BL = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Consecutive READ Bursts (BL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

READ/WRITE Interleave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Read Data Valid Window for x18 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

READ Burst with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

READ-NOP-READ with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Command Description in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Mode Register Definition in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

BURST REFRESH Operation with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Consecutive WRITE Bursts with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

WRITE-to-READ with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Consecutive READ Burst with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

JTAG Operation – Loading Instruction Code and Shifting Out Data . . . . . . . . . . . . . . . . . . . . . . . . . . .64

TAP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

PDF: 09005aef815b2df8/Source: 09005aef811ba111

288Mb_RLDRAM_II_SIOLOF.fm - Rev. O 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

288Mb: x18 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

List of Tables

Table 1:

Table 2:

Table 3:

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Table 5:

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Table 26:

Table 27:

16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA/FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Differential Input Clock Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Address and Command Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Data Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Cycle Time and READ/WRITE Latency Configuration Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

On-Die Termination DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Address Mapping in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode . . . . . . . . . . . . . .54

TAP Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

PDF: 09005aef815b2df8/Source: 09005aef811ba111

288Mb_RLDRAM_II_SIOLOT.fm - Rev. O 6/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18CHU-25 Related Products

	MT49H16M18CHU-25	MT49H16M18CFM-33	MT49H16M18CHU-33	MT49H16M18CHU-5	MT49H16M18CFM-25	MT49H16M18CFM-5
Description	DDR DRAM, 16MX18, 0.25ns, CMOS, PBGA144, FBGA-144	DDR DRAM, 16MX18, 0.3ns, CMOS, PBGA144, MICRO, BGA-144	DDR DRAM, 16MX18, 0.3ns, CMOS, PBGA144, FBGA-144	DDR DRAM, 16MX18, 0.5ns, CMOS, PBGA144, FBGA-144	DDR DRAM, 16MX18, 0.25ns, CMOS, PBGA144, MICRO, BGA-144	DDR DRAM, 16MX18, 0.5ns, CMOS, PBGA144, MICRO, BGA-144
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	FBGA-144	MICRO, BGA-144	FBGA-144	FBGA-144	MICRO, BGA-144	MICRO, BGA-144
Contacts	144	144	144	144	144	144
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.25 ns	0.3 ns	0.3 ns	0.5 ns	0.25 ns	0.5 ns
Other features	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH
Maximum clock frequency (fCLK)	400 MHz	300 MHz	300 MHz	200 MHz	400 MHz	200 MHz
I/O type	SEPARATE	COMMON	SEPARATE	SEPARATE	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144
JESD-609 code	e0	e0	e0	e0	e0	e0
length	18.5 mm	18.5 mm	18.5 mm	18.5 mm	18.5 mm	18.5 mm
memory density	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	18	18	18	18	18	18
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	144	144	144	144	144	144
word count	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	16MX18	16MX18	16MX18	16MX18	16MX18	16MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	BGA	TBGA	TBGA	BGA	BGA
Encapsulate equivalent code	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	235	235	235	235	235	235
power supply	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	0.93 mm	1.2 mm	1.2 mm	0.93 mm	0.93 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal surface	TIN LEAD SILVER	Tin/Lead (Sn/Pb)	TIN LEAD SILVER	TIN LEAD SILVER	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30
width	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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