EN71NS032A0
EN71NS032A0
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
32 Megabit (2M x 16-bit) CMOS 1.8 Volt-only Burst Simultaneous
Operation, Multiplexed Flash Memory and
16 Megabit (1M x 16-bit) Pseudo Static RAM
Distinctive Characteristics
MCP Features
■
Power supply voltage of 1.7V to 1.95V
■
High performance
- 70 ns @ random access
- 7 ns @ burst access (108MHz)
■
Package
- 6.2 x 7.7 x 1.0mm 56 ball BGA
■
Operating Temperature
- 25°C to +85°C
General Description
EN71NS032A0 is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
■
■
Burst Simultaneous Operation, Multiplexed NOR Flash Memory.
Burst Mode, Multiplexed Pseudo SRAM.
For detailed specifications, Please refer to the individual datasheets listed in the following table.
Device
NOR Flash Memory
Pseudo SRAM
Document
EN29NS032
ENPSS16
Flash Density
Flash Access time
Flash Burst mode
max frequency
Package
32Mb
70ns at Async. Mode
7ns at Burst Read
108MHz
56-ball BGA
pSRAM density
pSRAM Access time
pSRAM Burst mode
max frequency
16Mb
70ns at Async. Mode
7ns at Burst Read
108MHz
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. B, Issue Date: 2011/07/05
EN71NS032A0
Pin Description
Symbol
A20–A16
ADQ15–ADQ0
OE#
WE#
VSSQ/VSS
VCCQ/VCC
NC
Description
Address Inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the
Burst mode.
Write Enable input.
Ground
Device Power Supply (1.7 V–1.95 V).
Not Contact; pin not connected internally
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH”
configuration)
V
OL
= data invalid,
V
OH
= data valid.
Note: The default polarity for the pSRAM WAIT signal is
opposite the default polarity of the Flash RDY signal.
pSRAM WAIT (using default “Active HIGH” configuration)
V
OL
= data valid,
V
OH
= data invalid.
To match polarities, change bit 10 of the pSRAM Bus
Configruation Register to 0 (Active LOW WAIT). Alternately,
change bit 10 of the Flash Configuration Register to 0 (Active
LOW RDY)
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal
address counter. Should be at V
OL
or V
IH
while in
asynchronous mode.
Address Valid input. Indicates to device that the valid address
is present on the address inputs.
V
IL
= for asynchronous mode, indicates valid address; for
burst mode, causes starting address to be latched on rising
edge of CLK.
V
IH
= device ignores address inputs
Hardware reset input. V
IL
= device resets and returns to
reading array data
Hardware write protect input. V
IL
= disables program and
erase functions in the four outermost sectors. Should be at V
IH
for all other conditions.
Accelerated input. At Vpp , accelerates programming;
automatically places device in Accelerated Program mode. At
V
IL
, disables all program and erase functions. Should be at V
IH
for all other conditions. (Applying high voltage on MCP
package is prohibited; otherwise, internal RAM may be
damaged easily!)
Chip Enable Input for pSRAM.
Chip Enable Input for Flash. Asynchronous relative to CLK for
the Burst mode.
Control register enable (pSRAM).
Lower byte enable. DQ7~DQ0 (pSRAM)
Upper byte enable. DQ15~DQ8 (pSRAM)
Reserved for Future Use
Flash
pSRAM
●
●
●
●
●
●
●
●
●
●
●
●
●
●
RDYf/WAITp
●
●
CLK
●
●
AVD#
●
●
RESET# f
WP#f
●
●
Vppf
●
●
●
●
●
●
CE# p
CE# f
CREp
LB#p
UB#p
RFU
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. B, Issue Date: 2011/07/05
EN71NS032A0
Operating Mode (For Asynchronous mode)
Asynchronous Mode
BCR[15]=1
Read
Write
Standby
No operation
Configuration register
write
Configuration register
read
DPD
Power
Active
Active
Standby
Idle
Active
Active
Deep
Power-down
CLK ADV# CE# OE# WE# CRE
X
X
H or L
X
X
X
L
X
X
X
L
L
H
L
L
L
H
L
X
X
X
H
L
X
H
L
X
X
L
H
X
L
L
L
L
H
H
X
UB#/
A/DQ[15:0
WAIT2
LB#
]
L
L
X
X
X
L
X
Low-z
High-z
High-z
Low-z
Low-z
Low-z
High-z
Data out
Data in
High-z
X
High-z
Config.
Reg.out
High-z
Note
4
4
5, 6
4, 6
7
Operating Mode (For Synchronous Burst mode)
Burst Mode
BCR[15]=0
Async read
Async write
Standby
No operation
Initial burst read
Initial burst write
Power
Active
Active
Standby
Idle
Active
Active
CLK ADV# CE# OE# WE# CRE
H or L
H or L
H or L
H or L
X
X
L
L
L
L
H
L
L
L
L
X
X
X
X
H
H
L
X
X
H
L
L
L
L
L
L
L
UB#/
LB#
L
L
X
X
L
X
WAIT A/DQ[15:0] Note
Low-z
High-z
High-z
Low-z
Low-z
Low-z
Data out
Data in
High-z
X
Address
Address
Data out
or
Data in
High-z
Config.
Reg.out
High-z
4, 8
4
5, 6
4, 6
4, 9
4, 9
Burst continue
Configuration register
write
Configuration register
read
DPD
Active
H
L
X
X
X
L
Low-z
4, 9
Active
Active
Deep
Power-down
L
L
L
X
L
L
H
H
L
X
L
H
X
H
H
X
X
L
X
Low-z
Low-z
High-z
9. 10
9, 10
7
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. B, Issue Date: 2011/07/05
Training Edition
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