EN25Q80A
EN25Q80A
8 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
•
Single power supply operation
- Full voltage range: 2.7-3.6 volt
•
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
•
8 M-bit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
•
-
-
-
•
-
-
-
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#
Dual SPI: CLK, CS#, DQ
0
, DQ
1
, WP#
Quad SPI: CLK, CS#, DQ
0
, DQ
1
, DQ
2
, DQ
3
High performance
100MHz clock rate for one data bit
80MHz clock rate for two data bits
80MHz clock rate for four data bits
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
-
-
-
-
High performance program/erase speed
Page program time: 1.3ms typical
Sector erase time: 90ms typical
Block erase time 500ms typical
Chip erase time: 8 seconds typical
•
Lockable 256 byte OTP security sector
•
Minimum 100K endurance cycle
•
-
-
-
-
-
Package Options
8 pins SOP 150mil body width
8 pins SOP 200mil body width
8 contact VDFN
8 pins PDIP
All Pb-free packages are RoHS compliant
•
Low power consumption
- 12 mA typical active current
- 1
μA
typical power down current
•
-
-
-
Uniform Sector Architecture:
256 sectors of 4-Kbyte
16 blocks of 64-Kbyte
Any sector or block can be erased individually
•
Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q80A is an 8 Megabit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q80A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ
0
(DI),
DQ
1
(DO), DQ
2
(WP#) and DQ
3
(NC). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the
Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The EN25Q80A is designed to allow either single
Sector/Block
at a time or full chip erase operation. The
EN25Q80A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector
or block
.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. F, Issue Date: 2011/07/14
EN25Q80A
Figure.1 CONNECTION DIAGRAMS
CS#
DO (DQ
1
)
WP# (DQ
2
)
VSS
1
2
3
4
8
7
6
5
VCC
NC (DQ
3
)
CLK
DI (DQ
0
)
8 - LEAD SOP / PDIP
CS#
DO (DQ
1
)
WP# (DQ
2
)
VSS
1
2
3
4
8
7
6
5
VCC
NC (DQ
3
)
CLK
DI (DQ
0
)
8 - LEAD VDFN
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. F, Issue Date: 2011/07/14
EN25Q80A
Figure 2. BLOCK DIAGRAM
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
0
~ DQ
3
are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. F, Issue Date: 2011/07/14
EN25Q80A
Table 1. Pin Names
Symbol
CLK
DI (DQ
0
)
DO (DQ
1
)
CS#
WP# (DQ
2
)
NC(DQ
3
)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0)
*1
*1
Serial Data Output (Data Input Output 1)
Chip Enable
Write Protect (Data Input Output 2)
Not Connect (Data Input Output 3)
Supply Voltage (2.7-3.6V)
Ground
No Connect
*2
*2
Note:
1. DQ
0
and DQ
1
are used for Dual and Quad instructions.
2. DQ
0
~ DQ
3
are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ
0
, DQ
1
, DQ
2
, DQ
3
)
The EN25Q80A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ
0
, DQ
1
, DQ
2
and DQ
3
) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ
2
) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. F, Issue Date: 2011/07/14
EN25Q80A
MEMORY ORGANIZATION
The memory is organized as:
1,048,576 bytes
Uniform Sector Architecture
16 blocks of 64-Kbyte
256 sectors of 4-Kbyte
4096 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture (Continued)
Block
15
Sector
255
….
240
239
….
14
224
223
….
13
208
207
….
12
192
191
….
11
176
175
….
10
160
159
….
9
144
143
….
8
128
127
….
7
112
111
….
6
96
95
….
5
80
79
….
4
64
63
….
3
48
47
….
2
32
31
….
1
16
15
….
4
3
2
1
0
Address range
0FF000h
….
0F0000h
0EF000h
….
0E0000h
0DF000h
….
0D0000h
0CF000h
….
0C0000h
0BF000h
….
0B0000h
0AF000h
….
0A0000h
09F000h
….
090000h
08F000h
….
080000h
07F000h
….
070000h
06F000h
….
060000h
05F000h
….
050000h
04F000h
….
040000h
03F000h
….
030000h
02F000h
….
020000h
01F000h
….
010000h
00F000h
….
004000h
003000h
002000h
001000h
000000h
0FFFFFh
0F0FFFh
0EFFFFh
0E0FFFh
0DFFFFh
0D0FFFh
0CFFFFh
0C0FFFh
0BFFFFh
0B0FFFh
0AFFFFh
0A0FFFh
09FFFFh
090FFFh
08FFFFh
080FFFh
07FFFFh
070FFFh
06FFFFh
060FFFh
05FFFFh
050FFFh
04FFFFh
040FFFh
03FFFFh
030FFFh
02FFFFh
020FFFh
01FFFFh
010FFFh
00FFFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
….
©2004 Eon Silicon Solution, Inc.,
….
….
….
….
….
….
….
….
….
….
….
….
….
….
….
0
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
www.eonssi.com
Rev. F, Issue Date: 2011/07/14
Discrete Device
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