Datasheet
Tsi206 Primary Side Monitor with Inrush
Control
Features
•
•
•
•
•
•
•
•
•
•
•
•
Input voltage measurement (24 V or 48 V)
10-bit analog-to-digital converter (ADC)
Input voltage measurement accuracy 0.5%
Control of inrush current
Fuse status monitoring, high and low side
Primary current sensing and measurement
Primary side undervoltage, overvoltage and
brownout detection
Electronic circuit breaker function
Enable control for intermediate bus power
converter
Isolated PI-Link interface to secondary side
controller transmits primary voltage, current,
fuse status and input status data
Input UV shutdown accuracy <1%
Self-powered from 24 V or 48 V nominal
•
•
Industrial controllers
Single board computers
Description
The Tsi206 is designed to monitor parameters on
the high voltage primary side of an on-card power
system in a distributed power architecture.
In a typical 24 V or 48 V application, the Tsi206
measures input voltage and current and transmits
the digitized values through the PI-Link interface to
the secondary side controller (Tsi257). It also
controls an external MOSFET to limit card inrush
current at startup. Programmable input overvoltage
(OV) and undervoltage (UV) detection are provided.
The Tsi206 provides on-off control for an isolated
power converter that supplies the intermediate bus
voltage for the card. It monitors the status of up to
four input fuses, both high side and low side. Fuse
status information is transmitted to the secondary
side through the serial PI-Link interface.
Applications
•
•
Telecom and datacom cards
ATCA (Advanced Telecom Compute
Architecture) systems
Figure 1 — Typical application circuit
+
+
0V
(Battery
return
)
R5
R3
R4
R17
Tsi206
OP1
ENABLE
VDD
VDDO
TX_H
Power connections
shown as
C4
R19
EMI
filter
Enable
Intermediate
bus (IB) brick
IB rail
-
-
Card connector pins
R1 R2
Seat
(short pins
)
SHUNT
SEAT
CT
R16
TX_L
BUSOFF
R21
VCTRL
FETA
C7
C6
OP2
R13
Q2
UV
VBATT
FUSE_H
SENSE_P
SENSE_OUT
SENSE_IN
Brick
shutdown
signal
from
Tsi257
C11
FUSE_L
R15
R22
R14
Monitor
signal
to
Tsi257
T1
C2
R20
Q1
R18
C5
Isolation
circuit
(see Fig. 7)
R8
R6
R7
R9
-48 V A
Fuse A
Fuse B
NC
VBG
VSS
SENSE_N
POR
BIAS
R12
R10
VSSO
AUX
D1
C3
C1
R11
Primary
Secondary
-48 V B
D2
MD533J
Note:
High-side fuse monitoring is not shown – refer to Figure 8.
80C7000_MA001_01 April 2006
© Tundra Semiconductor Corporation
-1-
Tsi206 Primary Side Monitor with Inrush Control
Datasheet
Absolute maximum ratings
Table 1 lists the absolute maximum ratings.
St r e s s e s o u t s i d e t h e s e l i m i t s m a y c a u s e
permanent damage to the Tsi206. Exposure to any
Table 1 — Absolute maximum ratings
Parameter
Maximum input voltage
Current into any pin
Power dissipation (continuous)
Operating temperature range
Junction temperature
Storage temperature
Lead temperature
Soldering temperature
ESD rating (JESD22-A114-B, HBM)
(soldering, 10 seconds)
Peak body temperature for reflow
TA = 70°C
Condition
Relative to V
SS
Rating
-0.3 V to (V
DD
+ 0.3) V
5 mA
600 mW
-40°C to +85°C
+150°C
-65°C to +150°C
+300°C
260°C
2000 V
absolute maximum rating for extended periods can
affect the Tsi206 performance and reliability.
Recommended operating conditions
Table 2 recommended operating conditions. The
performance is guaranteed within these conditions.
Table 2 — Recommended operating conditions
Parameter
Operating voltage VDD (set by internal shunt regulator)
Bypass capacitor
Power-on reset capacitor
Operating temperature range
Condition
Relative to V
SS
V
DD
to V
SS
POR to V
SS
Rating
+3.3 V nominal
1
μ
F
47 nF
-40°C to +85°C
The Tsi206 is ESD sensitive, so normal ESD
handling precautions are recommended.
-2-
© Tundra Semiconductor Corporation
80C7000_MA001_01 April 2006
Datasheet
Tsi206 Primary Side Monitor with Inrush Control
Figure 2 — Pin assignments
BUSOFF
SEAT
FETA
BIAS
POR
VDD
25
24 VSS
23 SHUNT
22 SENSE_N
21 SENSE_OUT
20 SENSE_P
19 IC_VSS
18 IC_VSS
17 IC_VDD
9
IC_VSS
10
VCTRL
11
VSS
12
TX_H
13
VSSO
14
VDDO
15
TX_L
16
NC
VBG
32
UV
FUSE_H
FUSE_L
VBATT
SENSE_IN
AUX
IC_VSS
ENABLE
1
2
3
4
5
6
7
8
31
30
29
28
27
26
Tsi206
CT
32-pin LQFP
MD528B
Table 3 — DC characteristics
Parameter
Power supplies
V
DD
(set by internal shunt
regulator)
Supply current
V
DD
Temp = -40°C to 125°C
SHUNT pin connected to
VDD pin
Shunt regulator drawing
minimum current
Serial link operating, brick
enabled
3.2
3.3
3.4
V
Symbol
Conditions
Min
Typ
Max
Unit
I
DD
—
—
4
mA
Shunt regulator current
Recommended external
resistor (R5 in Figure 1)
Startup response time
I
SR
Supply voltage range 32 V
to 85 V
Supply voltage = 50 V, rise
time = 10 ns;
C1 = 1
μ
F; R5 = 6.2 k
Ω
—
—
—
—
6.2
600
40
—
1000
mA
k
Ω
μ
s
Undervoltage, overvoltage detection
OV threshold
Brownout threshold
UV comparator threshold
UV hysteresis
(Sheet 1 of 4)
V
OVH
V
BOL
V
UVT
Voltage at pin VBATT
Input voltage rising
Voltage at pin UV
Input voltage decreasing
UV pin voltage
increasing/decreasing
See below for UV hysteresis
2.37
1.3
1.24
2.39
1.31
1.25
1
2.42
1.32
1.26
V
V
V
80C7000_MA001_01 April 2006
© Tundra Semiconductor Corporation
-3-
Tsi206 Primary Side Monitor with Inrush Control
Datasheet
Table 3 — DC characteristics (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Undervoltage shutdown and startup (voltage at input rail)
UV low threshold
(shutdown)
UV high threshold
(startup)
V
UVL
V
UVH
Voltage at input rail
Input voltage decreasing
Voltage at input rail
Input voltage increasing
Set by R3 and R9
V
UVL
= V
UV
× (R3 + R9)/R9
Programmed by R3
V
UVH
= V
UVL
+ (I
UVHY
× R3)/
V
V
1000 (R3 expressed in k
Ω
)
UV hysteresis
V
UVHY
Voltage at input rail
Programmed by R3
Programmed by R3
V
UVHY
= (I
UVHY
× R3)/1000
(R3 expressed in k
Ω
)
9.9
11
V
Hysteresis current sink
Current sense amplifier
Output range
Input range
I
UVHY
UV shutdown condition
12.1
μ
A
V
ISENSE
V
CM
Voltage at SENSE_OUT
pin
Voltage between SENSE_N
and SENSE_P input pins
and V
SS
0.121
-0.1
—
—
2.377
2
V
V
Input offset
Input resistance
DC open loop gain
Unity gain bandwidth
V
OFFSET
R
IN
R
LOAD
>50 k
Ω
C
LOAD
< 50 pF
R
LOAD
>50 k
Ω
OC
OC
HY
Voltage at SENSE_IN pin
—
—
60
100
—
10
—
—
1
—
—
—
mV
M
Ω
dB
kHz
Overcurrent detection
threshold
Overcurrent hysteresis
Inrush current limiting
CT capacitor charge
current
CT capacitor discharge
current
CT trip high
CT trip low
Inrush complete
2.37
—
2.39
200
2.42
—
V
mV
I
CHARGE
I
DISCHARGE
V
REF_2
V
REF_1
V
FETA
Current limit time-out
Current limit retry delay
45
0.9
1.99
0.49
50
1
2
0.5
1.25
55
1.1
2.01
0.51
1.26
μ
A
μ
A
V
V
V
Inrush complete is detected
when voltage between
FETA and V
SS
pins
exceeds this threshold
1.24
(Sheet 2 of 4)
-4-
© Tundra Semiconductor Corporation
80C7000_MA001_01 April 2006
Datasheet
Tsi206 Primary Side Monitor with Inrush Control
Table 3 — DC characteristics (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Digital pin voltage levels (except pins TX_H, TX_L)
Output low
Output high
Input low
Input high
V
OL
V
OH
V
IL
V
IH
I
OH
= 1 mA
I
OH
= -1 mA
—
—
-0.3
2.0
0.07
3.25
—
—
—
—
0.96
5.25
V
V
V
V
PI-Link transmit datalink (pins TX_H, TX_L)
TX_H to TX_L differential
voltage - both driving
logic one
TX_H to TX_L differential
voltage - both drive logic
one
TX_H to TX_L differential
voltage - both drive logic
zero
TX_H to TX_L differential
voltage - both drive logic
zero
TX_H to TX_L differential
voltage - TX_H drives
zero, TX_L drives one
TX_H to TX_L differential
voltage - TX_H drives
zero, TX_L drives one
TX_H to TX_L differential
voltage - TX_H drives
one, TX_L drives zero
TX_H to TX_L differential
voltage - TX_H drives
one, TX_L drives zero
V
DIFF(11+)
I
TXH
= +100 mA
I
TXL
= +300 mA
I
TXH
= -100 mA
I
TXL
= -300 mA
I
TXH
= +100 mA
I
TXL
= +300 mA
I
TXH
= -100 mA
I
TXL
= -300 mA
I
TXH
= +100 mA
I
TXL
= +300 mA
I
TXH
= -100 mA
I
TXL
= -300 mA
I
TXH
= +100 mA
I
TXL
= +300 mA
I
TXH
= -100 mA
I
TXL
= -300 mA
-0.2
—
0.2
Vdiff
V
DIFF(11-)
-0.2
—
0.2
Vdiff
V
DIFF(00+)
-0.2
—
0.2
Vdiff
V
DIFF(00-)
-0.2
—
0.2
Vdiff
V
DIFF(01+)
-1.4
—
-4.0
Vdiff
V
DIFF(01-)
-1.4
—
-4.0
Vdiff
V
DIFF(10+)
1.4
—
4.0
Vdiff
V
DIFF(10-)
1.4
—
4.0
Vdiff
Input voltage monitor (at input pins VBATT, VSENSE, AUX)
ADC resolution
ADC resolution
ADC resolution
(Sheet 3 of 4)
Voltage at VBATT and AUX
pins
Input current (voltage at
SENSE_IN pin)
Voltage at FUSE_H and
FUSE_L pins
10 bits
8 bits
8 bits
bits
bits
bits
80C7000_MA001_01 April 2006
© Tundra Semiconductor Corporation
-5-
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